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| rev. 4250e?can?12/04 1 features high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture ? 133 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers + peripheral control registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier non volatile program and data memories ? 128k bytes of in-system reprogrammable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits selectable boot size: 1k bytes, 2k bytes, 4k bytes or 8k bytes in-system programming by on-chip boot program (can, uart) true read-while-write operation ? 4k bytes eeprom (endurance: 100,000 write/erase cycles) ? 4k bytes internal sram ? up to 64k bytes optional external memory space ? programming lock for software security jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? programming flash (hardware isp), eeprom, lock & fuse bits ? extensive on-chip debug support can controller 2.0a & 2.0b ? 15 full message objects with separate identifier tags and masks ? transmit, receive, automatic reply and frame buffer receive modes ? 1mbits/s maximum transfer rate at 8 mhz ? time stamping, ttc & listening mode (spying or autobaud) peripheral features ? programmable watchdog timer with on-chip oscillator ? 8-bit synchronous timer/counter-0 10-bit prescaler external event counter output compare or 8-bit pwm output ? 8-bit asynchronous timer/counter-2 10-bit prescaler external event counter output compare or 8-bit pwm output 32khz oscillator for rtc operation ? dual 16-bit synchronous timer/counters-1 & 3 10-bit prescaler input capture with noise canceler external event counter 3-output compare or 16-bit pwm output output compare modulation ? 8-channel, 10-bit sar adc 8 single-ended channels 7 differential channels 2 differential channels with programmable gain at 1x, 10x, or 200x ? on-chip analog comparator ? byte-oriented two-wire serial interface ? dual programmable serial usart ? master/slave spi serial interface programming flash (hardware isp) special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? 8 external interrupt sources ? 5 sleep modes: idle, adc noise reduction, power-save, power-down & standby ? software selectable clock frequency ? global pull-up disable i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-lead qfn operating voltages ? 2.7 - 5.5v operating temperature ? industrial (-40c to +85c) maximum frequency ? 8 mhz at 2.7v - industrial range ? 16 mhz at 4.5v - industrial range 8-bit microcontroller with 128k bytes of isp flash and can controller at90can128
2 at90can128 4250e?can?12/04 description the at90can128 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the at90can128 achieves throughputs approaching 1 mips per mhz allowing the sys- tem designer to optimize power consumption versus processing speed. the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the at90can128 provides the following features: 128k bytes of in-system program- mable flash with read-while-write capabilities, 4k bytes eeprom, 4k bytes sram, 53 general purpose i/o lines, 32 general purpose working registers, a can controller, real time counter (rtc), four flexible timer/counters with compare modes and pwm, 2 usarts, a byte oriented two-wire seri al interface, an 8-channel 10-bit adc with optional differential input stage with programmable gain, a programmable watchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi/can ports and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next inter- rupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. the device is manufactured using atmel?s high-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conv entional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel at90can128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the at90can128 avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, in- circuit emulators, and evaluation kits. applications that use the atmega128 avr microcontroller can be made compatible to use the at90can128, refer to application note avr 096, on the atmel web site. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 3 at90can128 4250e?can?12/04 block diagram figure 1. block diagram program counter stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. port b data dir. reg. port e data dir. reg. port a data dir. reg. port d data register port b data register port e data register port a data register port d interrupt unit eeprom spi usart0 status register z y x alu port b drivers port e drivers port a drivers port f drivers port d drivers port c drivers pb7 - pb0 pe7 - pe0 pa7 - pa0 pf7 - pf0 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comp arator pc7 - pc0 internal oscillator watchdog timer 8-bit data bus avcc usart1 timing and control oscillator oscillator calib. osc data dir. reg. port c data register port c on-chip debug jtag tap programming logic boundary- scan data dir. reg. port f data register port f adc por - bod reset pd7 - pd0 data dir. reg. port g data reg. port g port g drivers pg4 - pg0 two-wire serial interface can controller 4 at90can128 4250e?can?12/04 pin configurations figure 2. pinout at90can128- tqfp pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 (2) (2) nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) nc (1) at90can128 (64-lead tqfp top view) index corner 5 at90can128 4250e?can?12/04 figure 3. pinout at90can128- qfn pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 33 15 47 46 48 45 44 43 42 41 40 39 38 37 36 35 34 (2) (2) nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) nc (1) 17 18 20 19 21 22 23 24 25 26 27 29 28 32 31 30 52 51 50 49 64 63 62 53 61 60 59 58 57 56 55 54 at90can128 (64-lead qfn top view) index corner 6 at90can128 4250e?can?12/04 pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the at90can128 as listed on page 69. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the at90can128 as listed on page 71. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the at90can128 as listed on page 73. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of vari ous special features of the at90can128 as listed on page 75. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the at90can128 as listed on page 78. port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up 7 at90can128 4250e?can?12/04 resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. port f also serves the functions of the jtag interface. if the jtag interface is enabled, the pull-up resistors on pins pf7(tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. port g (pg4..pg0) port g is a 5-bit i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the at90can128 as listed on page 83. reset reset input. a low level on this pin for longer than the minimum pulse length will gener- ate a reset. the minimum pulse length is given in caracteristics. shorter pulses are not guaranteed to generate a reset. the i/o ports of the avr are immediately reset to their initial state even if the clock is not running. the clock is needed to reset the rest of the at90can128. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. avcc avcc is the supply voltage pin for the a/d converter on port f. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref this is the analog reference pin for the a/d converter. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit defini- tions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentation for more details. 8 at90can128 4250e?can?12/04 avr cpu core introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program ex ecution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. architectural overview figure 4. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being exe- cuted, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in- system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu operation, two operands are output from the register file, flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 9 at90can128 4250e?can?12/04 the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash pro- gram memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a con- stant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sect ions have dedicated lock bits for write and read/write protection. the spm (store program memory) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher is the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the at90can128 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-func- tions. some implementations of the archit ecture also provide a powerful multiplier supporting both signed/unsigned mult iplication and fractional fo rmat. see the ?instruc- tion set? section for a detailed description. 10 at90can128 4250e?can?12/04 status register the status register contains information about the result of the most recently executed arithmetic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: bit 7 ? i: global interrupt enable the global interrupt enable bit must be se t to enabled the interrupts. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i- bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the ?instruction set description? for detailed information. bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 11 at90can128 4250e?can?12/04 bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruc- tion set description? for detailed information. general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: one 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input one 16-bit output operand and one 16-bit result input figure 5 shows the structure of the 32 general purpose working registers in the cpu. figure 5. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 5, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being phys- ically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. the x-register, y-register, and z-register the registers r26..r31 have some added fu nctions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 6. figure 6. the x-, y-, and z-registers 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 12 at90can128 4250e?can?12/04 in the different addressing modes these addr ess registers have functions as fixed dis- placement, automatic increment, and automatic decrement (see the instruction set reference for details). ram page z select register ? rampz bits 7..2 ? res: reserved bits these are reserved bits and will always read as zero. when writing to this address loca- tion, write these bits to zero for compatibility with future devices. bit 1 ? rampz0: extended ram page z-pointer the rampz register is normally used to se lect which 64k ram page is accessed by the z-pointer. as the at90can128 does not support more than 64k of sram memory, this register is used only to select which page in the program memory is accessed when the elpm/spm instruction is used. the different settings of the rampz0 bit have the following effects: note that lpm is not affected by the rampz setting. stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer regis- ter always points to the top of the stack. note that the stack is implemented as growing from higher memory locations to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the num- ber of bits actually used is implementation dependent. note that the data space in some 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? rampz0 rampz read/write r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 rampz0 = 0: program memory address 0x0000 - 0x7fff (lower 64k bytes) is accessed by elpm/spm rampz0 = 1: program memory address 0x8000 - 0xffff (higher 64k bytes) is accessed by elpm/spm 13 at90can128 4250e?can?12/04 implementations of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. instruction execution timing this section describes the general access timing concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 7 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelin- ing concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 7. the parallel instruction fetches and instruction executions figure 8 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 8. single cycle alu operation reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together bit 151413121110 9 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2 nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time r egister operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 14 at90can128 4250e?can?12/04 with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory programming? on page 325 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 56. the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 56 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-programming? on page 311. interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user software can write logic one to the i-bit to enable nested inter- rupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remem- bered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the cor- responding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disap- pears before the interrupt is enabled, the interrupt will not be triggered. when the avr exits from an interrupt, it will always return to the main program and exe- cute one more instruction before any pending interrupt is served. note that the status register is not automatically stored when entering an interrupt rou- tine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable in terrupts, the interrupts will be immediately disabled. no interrupt will be executed after the cli instruction, even if it occurs simulta- neously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. 15 at90can128 4250e?can?12/04 when using the sei instruction to enable interrupts, the instruction following sei will be executed before any pending interrupts, as shown in this example. interrupt response time the interrupt execution response for all the enabled avr interrupts is four clock cycles minimum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine takes four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 17 at90can128 4250e?can?12/04 sram data memory figure 10 shows how the at90can128 sram memory is organized. the at90can128 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instruc- tions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower 1,280 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 4096 locations address the internal data sram. an optional external data sram can be used with the at90can128. this sram will occupy an area in the remaining address locations in the 64k address space. this area starts at the address following the internal sram. the register file, i/o, extended i/o and internal sram occupies the lowest 4352 bytes, so when using 64 kb (65,536 bytes) of external memory, 61,184 bytes of external memory are available. see ?exter- nal memory interface? on page 24 for details on how to take advantage of the external memory map. sram data access when the addresses accessing the sram me mory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. when the internal data memories are accessed, the read and write strobe pins (pg0 and pg1) are inactive during the whole access cycle. external sram operation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycle. if the stack is placed in external sram, interrupts, subroutine calls and returns take three clock cycles extra because the two-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access. when external sram interface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruc- tion set manual for one, two, and three wait-states. the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o regis- ters, and the 1,024 bytes of internal data sram in the at90can128 are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 11. 18 at90can128 4250e?can?12/04 figure 10. data memory map sram data access times this section describes the general access timing concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 11. figure 11. on-chip data sram access cycles 32 registers 64 i/o registers internal sram (4096 x 8) 0x0000 - 0x001 f 0x0020 - 0x005 f 0x1100 0x10ff 0xffff 0x0060 - 0x00f f data memory external sram (0 - 64k x 8) 160 ext i/o reg. 0x0100 clk wr rd data data a ddress address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 19 at90can128 4250e?can?12/04 eeprom data memory the at90can128 contains 4-kbytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see ?spi serial programming overview? on page 337, ?jtag programming overview? on page 342, and ?parallel programming overview? on page 329 respectively. eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 1. a self-timing function, how- ever, lets the user software detect when the next byte can be writt en. if the user code contains instructions that write the eepr om, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom corruption? on page 23 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be fol- lowed. refer to the description of the eeprom control register for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. the eeprom address registers ? eearh and eearl bits 15..12 ? reserved bits these bits are reserved bits in the at90can128 and will always read as zero. bits 11..0 ? eear11..0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 4-kbytes eeprom space. t he eeprom data bytes are addressed linearly between 0 and 4,095. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. the eeprom data register ? eedr bit 15 14 13 12 11 10 9 8 ? ? ? ? eear11 eear10 eear9 eear8 eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7654 3 2 10 read/write rrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 x x x x xxxx x x xx bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 20 at90can128 4250e?can?12/04 bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read oper- ation, the eedr contains the data read out from the eeprom at the address given by eear. the eeprom control register ? eecr bits 7..4 ? reserved bits these bits are reserved bits in the at90can128 and will always read as zero. bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant interrupt when eewe is cleared. bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to one causes the eeprom to be written. when eemwe is set, setting eewe within four clock cycles will write data to the eeprom at the selected address if eemwe is zero, setting eewe will have no effect. when eemwe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be written to one before a logical one is written to eewe, otherwise no eeprom wr ite takes place. the following procedure should be followed when writing the eepr om (the order of steps 3 and 4 is not essential): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program memory control and status register) becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writing a zero to eewe in eecr. 6. within four clock cycles after setting eemwe, write a logical one to eewe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming? on page 311 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the bit 76543 210 ? ? ? ? eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 0 21 at90can128 4250e?can?12/04 eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 1 lists the typical programming time for eeprom access from the cpu. note: 1. uses 1 mhz clock, independent of cksel fuse settings. table 1. eeprom programming time. symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 67 584 8.5 ms 22 at90can128 4250e?can?12/04 the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occu r during execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoing spm com- mand to finish. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 25 at90can128 4250e?can?12/04 figure 12. external memory with sector select using the external memory interface the interface consists of: ad7:0: multiplexed low-order address bus and data bus. a15:8: high-order address bus (configurable number of bits). ale: address latch enable. rd : read strobe. wr : write strobe. the control bits for the external memory interface are located in two registers, the exter- nal memory control register a ? xmcra, and the external memory control register b ? xmcrb. when the xmem interface is enabled, the xmem interface will override the setting in the data direction registers that corresponds to the ports dedicated to the xmem interface. for details about the port override, see the alternate functions in section ?i/o-ports? on page 61. the xmem interface will auto-detect whether an access is internal or external. if the access is external, the xmem interface will output address, data, and the control signals on the ports according to figure 14 (this figure shows the wave forms without wait-states). when ale goes from high-to-low, there is a valid address on ad7:0. ale is low during a data transfer. when the xmem interface is enabled, also an internal access will cause activity on address, data and ale ports, but the rd and wr strobes will not toggle during internal access. when the external memory interface is disabled, the nor- mal pin and data direction settings are used. note that when the xmem interface is disabled, the address space above the internal sram boundary is not mapped into the internal sram. figure 13 illustrates how to connect an external sram to the avr using an octal latch (typically ?74 x 573? or equivalent) which is transparent when g is high. 0x0000 0x10ff external memory (0-60k x 8) 0xffff internal memory srl[2..0] srw11 srw10 srw01 srw00 lower sector upper sector 0x1100 26 at90can128 4250e?can?12/04 address latch requirements due to the high-speed operation of the xram interface, the address latch must be selected with care for system frequencies above 8 mhz @ 4v and 4 mhz @ 2.7v. when operating at conditions above these frequencies, the typical old style 74hc series latch becomes inadequate. the external memory interface is designed in compliance to the 74ahc series latch. however, most latc hes can be used as long they comply with the main timing parameters. the main parameters for the address latch are: d to q propagation delay (t pd ). data setup time before g low (t su ). data (address) hold time after g low ( th ). the external memory interface is designed to guaranty minimum address hold time after g is asserted low of t h = 5 ns. refer to t laxx_ld /t llaxx_st in ?memory programming? tables 142 through tables 149. the d-to-q propagation delay (t pd ) must be taken into consideration when calculating the access time requirement of the external component. the data setup time before g low (t su ) must not exceed address valid to ale low (t av- llc ) minus pcb wiring delay (dependent on the capacitive load). figure 13. external sram connected to the avr pull-up and bus-keeper the pull-ups on the ad7:0 ports may be activated if the corresponding port register is written to one. to reduce power consumption in sleep mode, it is recommended to dis- able the pull-ups by writing the port register to zero before entering sleep. the xmem interface also provides a bus-keeper on the ad7:0 lines. the bus-keeper can be disabled and enabled in software as described in ?external memory control reg- ister b ? xmcrb? on page 30. when enabled, the bus-keeper will ensure a defined logic level (zero or one) on the ad7:0 bus when these lines would otherwise be tri-stated by the xmem interface. timing external memory devices have different timing requirements. to meet these require- ments, the at90can128 xmem interface provides four different wait-states as shown in table 3. it is important to consider the timing specification of the external memory device before selecting the wait-state. the most important parameters are the access time for the external memory compared to the set-up requirement of the at90can128. the access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. the access time cannot exceed the time from the ale pulse must be asserted low until data is stable during a read sequence (see t llrl + t rlrh - t dvrh in tables 142 through tables 149). the different wait-states are set up in software. as an additional feature, it is pos- sible to divide the external memory space in two sectors with individual wait-state d[7:0] a[7:0] a[15:8] rd wr sram dq g ad7:0 ale a15:8 rd wr avr 27 at90can128 4250e?can?12/04 settings. this makes it possible to connect two different memory devices with different timing requirements to the same xmem interface. for xmem interface timing details, please refer to tables 142 through tables 149 and figure 173 to figure 176 in the ?external data memory characteristics? on page 365. note that the xmem interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. the skew between the internal and external clock (xtal1) is not guarantied (varies between devices temperature, and sup- ply voltage). consequently, the xmem interface is not suited for synchronous operation. figure 14. external data memory cycles no wait-state (srwn1=0 and srwn0=0) (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t4 is only present if the next instruction accesses the ram (internal or external). figure 15. external data memory cycles with srwn1 = 0 and srwn0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t5 is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) xxxxx xxxxxxxx ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 28 at90can128 4250e?can?12/04 figure 16. external data memory cycles with srwn1 = 1 and srwn0 = 0 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t6 is only present if the next instruction accesses the ram (internal or external). figure 17. external data memory cycles with srwn1 = 1 and srwn0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t7 is only present if the next instruction accesses the ram (internal or external). xmem register description external memory control register a ? xmcra bit 7 ? sre: external sram/xmem enable writing sre to one enables the external memory interface.the pin functions ad7:0, a15:8, ale, wr , and rd are activated as the alternate pin functions. the sre bit over- ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 t6 bit 76543210 sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 29 at90can128 4250e?can?12/04 rides any pin direction settings in the respective data direction registers. writing sre to zero, disables the external memory interface and the normal pin and data direction set- tings are used. note that when the xmem interface is disabled, the address space above the internal sram boundary is not mapped into the internal sram. bit 6..4 ? srl2, srl1, srl0: wait-state sector limit it is possible to configure different wait-states for different external memory addresses. the external memory address space can be divided in two sectors that have separate wait-state bits. the srl2, srl1, and srl0 bits select the split of the sectors, see table 2 and figure 12. by default, the srl2, srl1, and srl0 bits are set to zero and the entire external memory address space is treated as one sector. when the entire sram address space is configured as one sector, the wait-states are configured by the srw11 and srw10 bits. bit 3..2 ? srw11, srw10: wait-state select bits for upper sector the srw11 and srw10 bits control the number of wait-states for the upper sector of the external memory address space, see table 3. bit 1..0 ? srw01, srw00: wait-state select bits for lower sector the srw01 and srw00 bits control the number of wait-states for the lower sector of the external memory address space, see table 3. table 2. sector limits with different settings of srl2..0 srl2 srl1 srl0 sector limits 000 lower sector = n/a upper sector = 0x1100 - 0xffff 001 lower sector = 0x1100 - 0x1fff upper sector = 0x2000 - 0xffff 010 lower sector = 0x1100 - 0x3fff upper sector = 0x4000 - 0xffff 011 lower sector = 0x1100 - 0x5fff upper sector = 0x6000 - 0xffff 100 lower sector = 0x1100 - 0x7fff upper sector = 0x8000 - 0xffff 101 lower sector = 0x1100 - 0x9fff upper sector = 0xa000 - 0xffff 110 lower sector = 0x1100 - 0xbfff upper sector = 0xc000 - 0xffff 111 lower sector = 0x1100 - 0xdfff upper sector = 0xe000 - 0xffff table 3. wait states (1) srwn1 srwn0 wait states 0 0 no wait-states 0 1 wait one cycle during read/write strobe 1 0 wait two cycles during read/write strobe 1 1 wait two cycles during read/write and wait one cycle before driving out new address 30 at90can128 4250e?can?12/04 note: 1. n = 0 or 1 (lower/upper sector). for further details of the timing and wait-states of the external memory interface, see figures 14 through figures 17 for how the setting of the srw bits affects the timing. external memory control register b ? xmcrb bit 7? xmbk: external memory bus-keeper enable writing xmbk to one enables the bus keeper on the ad7:0 lines. when the bus keeper is enabled, it will ensure a defined logic le vel (zero or one) on ad7:0 when they would otherwise be tri-stated. writing xmbk to zero disables the bus keeper. xmbk is not qualified with sre, so even if the xmem interface is disabled, the bus keepers are still activated as long as xmbk is one. bit 6..4 ? reserved bits these are reserved bits and will always read as zero. when writing to this address loca- tion, write these bits to zero for compatibility with future devices. bit 2..0 ? xmm2, xmm1, xmm0: external memory high mask when the external memory is enabled, all port c pins are default used for the high address byte. if the full 60kb address space is not required to access the external mem- ory, some, or all, port c pins can be released for normal port pin function as described in table 4. as described in ?using all 64kb locations of external memory? on page 31, it is possible to use the xmmn bits to access all 64kb locations of the external memory. bit 76543210 xmbk????xmm2xmm1xmm0xmcrb read/writer/wrrrrr/wr/wr/w initial value00000000 table 4. port c pins released as normal port pins when the external memory is enabled xmm2 xmm1 xmm0 # bits for external memory address released port pins 0 0 0 8 (full 60 kb space) none 0017 pc7 0 1 0 6 pc7 .. pc6 0 1 1 5 pc7 .. pc5 1 0 0 4 pc7 .. pc4 1 0 1 3 pc7 .. pc3 1 1 0 2 pc7 .. pc2 1 1 1 no address high bits full port c 31 at90can128 4250e?can?12/04 using all locations of external memory smaller than 64 kb since the external memory is mapped after the internal memory as shown in figure 12, the external memory is not addressed when addressing the first 4,352 bytes of data space. it may appear that the first 4,352 bytes of the external memory are inaccessible (external memory addresses 0x0000 to 0x10ff). however, when connecting an exter- nal memory smaller than 64 kb, for example 32 kb, these locations are easily accessed simply by addressing from address 0x8000 to 0x90ff. since the external memory address bit a15 is not connected to the external memory, addresses 0x8000 to 0x90ff will appear as addresses 0x0000 to 0x10ff for the external memory. addressing above address 0x90ff is not recommended, since this will address an external memory loca- tion that is already accessed by another (l ower) address. to the application software, the external 32 kb memory will appear as one linear 32 kb address space from 0x1100 to 0x90ff. this is illustrated in figure 18. figure 18. address map with 32 kb external memory using all 64kb locations of external memory since the external memory is mapped after the internal memory as shown in figure 12, only 60kb of external memory is available by default (address space 0x0000 to 0x10ff is reserved for internal memory). however, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. this can be done by using the xmmn bits and control by software the most significant bits of the address. by set- ting port c to output 0x00, and releasing the most significant bits for normal port pin operation, the memory interface will address 0x0000 - 0x1fff. see the following code examples. (unused) internal memory 0x0000 0 x1100 0 x10ff 0 xffff avr memory map external memory 0 x8000 0 x7fff 0 x9100 0 x90ff external 32k sram 0x000 0 0x110 0 0x10f f 0x7ff f 32 at90can128 4250e?can?12/04 note: 1. the example code assumes that the part specific header file is included. care must be exercised using this option as most of the memory is masked away. assembly code example (1) ; offset is defined to 0x2000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:5 ldi r16, (1< 34 at90can128 4250e?can?12/04 system clock clock systems and their distribution figure 19 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 43. the clock systems are detailed below. figure 19. clock distribution cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general purpose register file, the status reg- ister and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, spi, can, usart. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. also note that address recognition in the twi module is carried out asynchronously when clk i/o is halted, enabling twi address recep- tion in all sleep modes. flash clock ? clk flash the flash clock controls operation of the flash interface. the flash clock is usually active simultaneously with the cpu clock. asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/counter to be clocked directly from an external clock or an external 32 khz clock crystal. the dedicated clock general i/o modules can controller cpu core ram clk i/o clk asy avr clock control unit clk cpu flash and eeprom clk flash source clock watchdog timer watchdog oscillator reset logic prescaler clock multiplexer multiplexer ckout fuse c lko watchdog clock calibrated rc oscillator timer/counter2 oscillator external clock crystal oscillator low-frequency crystal oscillator external clock adc clk adc asynchronous timer/counter2 timer/counter2 tosc2 xtal2 tosc1 xtal1 35 at90can128 4250e?can?12/04 domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. adc clock ? clk adc the adc is provided with a dedicated cloc k domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accu- rate adc conversion results. clock sources the device has the following clock source opt ions, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. the various choices for each clocking option is given in the following sections. when the cpu wakes up from power-down or power-save, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. the watchdog oscillator is used for tim- ing this real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 6. the frequency of the watchdog oscillator is voltage dependent as shown in ?at90can128 typical characteristics? on page 374. default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is the intern al rc oscillator with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. table 5. device clocking options select (1) device clocking option cksel3..0 external crystal/ceramic resonator 1111 - 1000 external low-frequency crystal 0111 - 0100 calibrated internal rc oscillator 0010 external clock 0000 reserved 0011, 0001 table 6. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 64k (65,536) 36 at90can128 4250e?can?12/04 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillato r, as shown in figure 20. either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capac- itance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 7. for ceramic resonators, the capacitor values given by the manufacturer should be used. for more information on how to choose capacitors and other details on oscillator operation, refer to the multi- purpose oscillator application note. figure 20. crystal oscillator connections the oscillator can operate in three different modes, each optimized for a specific fre- quency range. the operating mode is selected by the fuses cksel3..1 as shown in table 7. notes: 1. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 8. table 7. crystal oscillator operating modes cksel3..1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (1) 0.4 - 0.9 12 - 22 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 xtal 2 xtal 1 gnd c2 c1 37 at90can128 4250e?can?12/04 notes: 1. these options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by se tting the cksel fuses to ?0100?, ?0101?, ?0110?, or ?0111?. the crystal should be connected as shown in figure 21. figure 21. low-frequency crystal oscillator connections 12-22 pf capacitors may be necessary if the parasitic impedance (pads, wires & pcb) is very low. table 8. start-up times for the oscillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 65 ms ceramic resonator, slowly rising power 010 1k ck (2) 14ck ceramic resonator, bod enabled 011 1k ck (2) 14ck + 4.1 ms ceramic resonator, fast rising power 100 1k ck (2) 14ck + 65 ms ceramic resonator, slowly rising power 1 01 16k ck 14ck crystal oscillator, bod enabled 1 10 16k ck 14ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 14ck + 65 ms crystal oscillator, slowly rising power xtal 2 xtal 1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz 38 at90can128 4250e?can?12/04 when this oscillator is selected, start-up times are determined by the sut1..0 fuses as shown in table 9 and cksel1..0 fuses as shown in table 10. note: 1. these options should only be used if frequency stability at start-up is not important for the application calibrated internal rc oscillator the calibrated internal rc oscillator provi des a fixed 8.0 mhz clock. the frequency is nominal value at 3v and 25 c. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse must be programmed in order to divide the internal frequency by 8 during start-up. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 41 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 11. if selected, it will operate with no external components. during reset, hard- ware loads the calibration byte into the osccal register and thereby automatically calibrates the rc oscillator. at 5v and 25 c, this calibration gives a frequency within 10% of the nominal frequency. using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve 2% accuracy at any given v cc and temperature. when this oscillator is used as the chip clock, the watch- dog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value, see the section ?calibration byte? on page 328. note: 1. the device is shipped with this option selected. table 9. start-up times for the low-frequency crystal oscillator clock selection sut1..0 additional delay from reset (v cc = 5.0v) recommended usage 00 14ck fast rising power or bod enabled 01 14ck + 4.1 ms slowly rising power 10 14ck + 65 ms stable frequency at start-up 11 reserved table 10. start-up times for the low-frequency crystal oscillator clock selection cksel3..0 start-up time from power-down and power-save recommended usage 0100 (1) 1k ck 0101 32k ck stable frequency at start-up 0110 (1) 1k ck 0111 32k ck stable frequency at start-up table 11. internal calibrated rc oscillator operating modes (1) cksel3..0 nominal frequency 0010 8.0 mhz 39 at90can128 4250e?can?12/04 when this oscillator is selected, start-up times are determined by the sut fuses as shown in table 12. note: 1. the device is shipped with this option selected. oscillator calibration register ? osccal bit 7 ? reserved bit this bit is reserved for future use. bits 6..0 ? cal6..0: oscillator calibration value writing the calibration byte to this address will trim the internal oscillator to remove pro- cess variations from the oscillator frequency. this is done automatically during chip reset. when osccal is zero, the lowest available frequency is chosen. writing non- zero values to this register will increase the frequency of the internal oscillator. writing 0x7f to the register gives the highest available frequency. the calibrated oscillator is used to time eeprom and flash access. if eeprom or flash is written, do not cali- brate to more than 10% above the nominal frequency. otherwise, the eeprom or flash write may fail. note that the oscillator is intended for calibration to 8.0 mhz. tuning to other values is not guaranteed, as indicated in table 13. external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 22. to run the device on an external clock, the cksel fuses must be pro- grammed to ?0000?. table 12. start-up times for the internal calibrated rc oscillator clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1 ms fast rising power 10 (1) 6 ck 14ck + 65 ms slowly rising power 11 reserved bit 76543210 ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 <----- ------ device specific calibration value ------ -----> table 13. internal rc oscillator frequency range. osccal value min frequency in percentage of nominal frequency max frequency in percentage of nominal frequency 0x00 50% 100% 0x3f 75% 150% 0x7f 100% 200% 40 at90can128 4250e?can?12/04 figure 22. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses as shown in table 15. when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to ensure that the mcu is kept in reset during such changes in the clock frequency. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. refer to ?system clock prescaler? on page 41 for details. clock output buffer when the ckout fuse is programmed, the system clock will be output on clko. this mode is suitable when chip clock is used to drive other circuits on the system. the clock will be output also during reset and the normal operation of i/o pin will be overridden when the fuse is programmed. any clock source, including internal rc oscillator, can be selected when clko serves as clock output. if the system clock prescaler is used, it is the divided system clock that is output (ckout fuse programmed). timer/counter2 oscillator for avr microcontrollers with timer/counter2 oscillator pins (tosc1 and tosc2), the crystal is connected directly between the pins. the oscillator is optimized for use with a 32.768 khz watch crystal. 12-22 pf capacitors may be necessary if the parasitic imped- ance (pads, wires & pcb) is very low. table 14. external clock frequency cksel3..0 frequency range 0000 0 - 16 mhz table 15. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1 ms fast rising power 10 6 ck 14ck + 65 ms slowly rising power 11 reserved xtal 2 xtal 1 gnd nc e xternal clock signal 41 at90can128 4250e?can?12/04 at90can128 share the timer/counter2 oscillator pins (tosc1 and tosc2) with pg4 and pg3. this means that both pg4 and pg3 can only be used when the timer/counter2 oscillator is not enable. applying an external clock source to tosc1 can be done in asynchronous operation if extclk in the assr register is written to logic one. see ?asynchronous operation of the timer/counter2? on page 154 for further description on selecting external clock as input instead of a 32 khz crystal. in this configuration, pg4 cannot be used but pg3 is available. system clock prescaler the at90can128 system clock can be divided by setting the clock prescaler register ? clkpr. this feature can be used to decrease power consumption when the require- ment for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 16. clock prescaler register ? clkpr bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable change of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. bit 6..0 ? reserved bits these bits are reserved for future use. bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchronous peripherals is reduced when a division factor is used. the divi- sion factors are given in table 16. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write pro- cedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unpro- grammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 42 at90can128 4250e?can?12/04 clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating condi- tions. the device is shipped with the ckdiv8 fuse programmed. note: when the system clock is divided, timer/counter0 can be used with asynchronous clock only. the frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down source clock. otherwise, interrupts may be lost, and accessing the timer/counter0 registers may fail. table 16. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 43 at90can128 4250e?can?12/04 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (i dle, adc noise reduction, power-down, power-save, or standby) will be activated by the sleep instruction. see table 17 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, exe- cutes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. figure 19 on page 34 presents the different clock systems in the at90can128, and their distribution. the figure is helpful in selecting an appropriate sleep mode. sleep mode control register ? smcr the sleep mode control register contains control bits for power management. bit 7..4 ? reserved bits these bits are reserved for future use. bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 17. note: 1. standby mode is only recommended for use with external crystals or resonators. bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one bit 76543210 ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value00000000 table 17. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 011power-save 100reserved 101reserved 1 1 0 standby (1) 111reserved 44 at90can128 4250e?can?12/04 just before the execution of the sleep instruction and to clear it immediately after wak- ing up. idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing spi, can, usart, analog comparator, adc, two-wire serial interface, timer/counters, watchdog, and the interrupt system to con- tinue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and sta- tus register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, the two-wire serial interface address watch, timer/counter2, can and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measure- ments. if the adc is enabled, a conversi on starts automatically when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a two-wire serial interface address match inter- rupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level interrupt on int7:4, or an external interrupt on int3:0 can wake up the mcu from adc noise reduction mode. power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, the external oscillator is stopped, while the external interrupts, the two-wire serial interf ace address watch, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, a two-wire serial interface address match interrupt, an external level interrupt on int7:4, or an external interrupt on int3:0 can wake up the mcu. this sleep mode basi- cally halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external inter- rupts? on page 88 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 35. power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identical to power-down, with one exception: if timer/counter2 is clocked asynchronously, i.e., the as2 bit in assr is set, timer/counter2 will run during sleep. the device can wake up from either timer over- flow or output compare event from timer/counter2 if the corresponding 45 at90can128 4250e?can?12/04 timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if the asynchronous timer is not clocked asynchronously, power-down mode is rec- ommended instead of power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in power-save mode if as2 is 0. this sleep mode basically halts all clocks except clk asy , allowing operation only of asyn- chronous modules, including timer/counter2 if clocked asynchronously. standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in 6 clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if as2 bit in assr is set. 3. only int3:0 or level interrupt int7:4. minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device?s functions are operating. all functions not needed should be dis abled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?analog to digital con- verter - adc? on page 265 for details on adc operation. analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage ref- erence will be enabled, independent of sleep m ode. refer to ?analog comparator? on page 262 for details on how to configure the analog comparator. table 18. active clock domains and wake-up sources in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc enabled int7:0 twi address match timer2 spm/ eeprom ready adc other i/o idle x x x x x (2) xxxxxx adc noise reduction x x x x (2) x (3) xx (2) xx power-down x (3) x power-save x (2) x (2) x (3) xx (2) standby (1) xx (3) x 46 at90can128 4250e?can?12/04 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?brown-out detec- tion? on page 50 for details on how to configure the brown-out detector. internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detec- tion, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be con- suming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt age reference? on page 52 for details on the start-up time. watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep mo des, this will contribute significantly to the total current consumption. refer to ?watchdog timer? on page 53 for details on how to configure the watchdog timer. port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buff- ers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 65 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause signi ficant current even in active mode. digital input buffers can be disabled by writing to the digital input disable regis- ters (didr1 and didr0). refer to ?digital input disable register 1 ? didr1? on page 264 and ?digital input disable register 0 ? didr0? on page 283 for details. jtag interface and on-chip debug system if the on-chip debug system is enabled by ocden fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. in the deeper sleep modes, this will contribute significantly to the total current consumption. there are three alternative ways to avoid this: disable ocden fuse. disable jtagen fuse. write one to the jtd bit in mcucsr. the tdo pin is left floating when the jtag interface is enabled while the jtag tap controller is not shifting data. if the hardware connected to the tdo pin does not pull up the logic level, power consumption will increase. note that the tdi pin for the next device in the scan chain contains a pull-up that avoids this problem. writing the jtd bit in the mcucsr register to one or leaving the jtag fuse unprogrammed disables the jtag interface. 47 at90can128 4250e?can?12/04 system control and reset resetting the avr during reset, all i/o registers are set to their initial values, and the program starts exe- cution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 23 shows the reset logic. table 19 defines the electrical param- eters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the different selections for the delay period are presented in ?clock sources? on page 35. reset sources the at90can128 has five sources of reset: power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system. refer to the section ?boundary-scan ieee 1149.1 (jtag)? on page 290 for details. 48 at90can128 4250e?can?12/04 figure 23. reset logic notes: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling) mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor jtrf jtag reset register watchdog oscillator sut[1:0] power-on reset circuit table 19. reset characteristics symbol parameter condition min. typ. max. units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (1) 1.3 2.3 v v rst reset pin threshold voltage 0.2 v cc 0.85 v cc v t rst minimum pulse width on reset pin vcc = 5 v, temperature = 25 c 400 ns 49 at90can128 4250e?can?12/04 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is defined in table 19. the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reach- ing the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 24. mcu start-up, reset tied to v cc figure 25. mcu start-up, reset extended externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 19) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. v reset time-out i nternal reset t tout v pot v rst cc reset t ime-out i nternal reset t tout v pot v rst v cc 50 at90can128 4250e?can?12/04 figure 26. external reset during operation brown-out detection at90can128 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. the test is performed using bodlevel = 010 for low operating voltage and bodlevel = 101 for high operating voltage . when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 27), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 27), the delay counter starts the mcu after the time- out period t tout has expired. cc table 20. bodlevel fuse coding (1) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 4.1 v 101 4.0 v 100 3.9 v 011 3.8 v 010 2.7 v 001 2.6 v 000 2.5 v table 21. brown-out characteristics symbol parameter min. typ. max. units v hyst brown-out detector hysteresis 70 mv t bod min pulse width on brown-out reset 2 s 51 at90can128 4250e?can?12/04 the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 19. figure 27. brown-out reset during operation watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 53 for details on operation of the watchdog timer. figure 28. watchdog reset during operation mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. bit 7..5 ? reserved bits these bits are reserved for future use. v cc reset time-out i nternal reset v bot- v bot+ t tout ck cc bit 76543210 ? ? ? jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 52 at90can128 4250e?can?12/04 bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset by a power-on reset, or by writing a logic zero to the flag. bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identif y a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. internal voltage reference at90can128 features an internal bandgap reference. this reference is used for brown- out detection, and it can be used as an input to the analog comparator or the adc. voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 22. to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the bodlevel [2..0] fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog com- parator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 53 at90can128 4250e?can?12/04 voltage reference characteristics watchdog timer the watchdog timer is clocked from a separate on-chip oscillator which runs at 1 mhz. this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 24 on page 54. the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a chip reset occurs. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at90can128 resets and executes from the reset vector. for tim- ing details on the watchdog reset, refer to table 24 on page 54. to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 23. refer to ?timed sequences for changing the configuration of the watchdog timer? on page 55 for details. figure 29. watchdog timer table 22. internal voltage reference characteristics symbol parameter condition min. typ. max. units v bg bandgap reference voltage 1.0 1.1 1.2 v t bg bandgap reference start-up time 40 70 s i bg bandgap reference current consumption 15 a table 23. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled timed sequence timed sequence programmed 2 enabled always enabled timed sequence watchdog oscillator ~1 mhz 54 at90can128 4250e?can?12/04 watchdog timer control register ? wdtcr bits 7..5 ? reserved bits these bits are reserved bits for future use. bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is written to logic zero. otherwise, the watchdog will not be disabled. once written to one, har dware will clear this bit after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. this bit must also be set when changing the pr escaler bits. see ?timed sequences for changing the configuration of the watchdog timer? on page 55 bit 3 ? wde: watchdog enable when the wde is written to logic one, the watchdog timer is enabled, and if the wde is written to logic zero, the watchdog timer function is disabled. wde can only be cleared if the wdce bit has logic level one. to disable an enabled watchdog timer, the follow- ing procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic 0 to wde. this disables the watchdog. in safety level 2, it is not possible to di sable the watchdog timer, even with the algo- rithm described above. see ?timed sequences for changing the configuration of the watchdog timer? on page 55 bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1, and 0 the wdp2, wdp1, and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 24. bit 76543210 ? ? ? wdce wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value00000000 table 24. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 17.1 ms 16.3 ms 0 0 1 32k cycles 34.3 ms 32.5 ms 0 1 0 64k cycles 68.5 ms 65 ms 0 1 1 128k cycles 0.14 s 0.13 s 1 0 0 256k cycles 0.27 s 0.26 s 1 0 1 512k cycles 0.55 s 0.52 s 1 1 0 1,024k cycles 1.1 s 1.0 s 1 1 1 2,048k cycles 2.2 s 2.1 s 55 at90can128 4250e?can?12/04 the following code example shows one assembly and one c function for turning off the wdt. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: 1. the example code assumes that the part specific header file is included. timed sequences for changing the configuration of the watchdog timer the sequence for changing configuration differs slightly between the two safety levels. separate procedures are described for each level. safety level 1 in this mode, the watchdog timer is initially disabled, but can be enabled by writing the wde bit to 1 without any restriction. a timed sequence is needed when changing the watchdog time-out period or disabling an enabled watchdog timer. to disable an enabled watchdog timer, and/or changing the watchdog time-out, the following proce- dure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, in the same operation, write the wde and wdp bits as desired, but with the wdce bit cleared. safety level 2 in this mode, the watchdog timer is always enabled, and the wde bit will always read as one. a timed sequence is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: 1. in the same operation, write a logical one to wdce and wde. even though the wde always is set, the wde must be written to one to start the timed sequence. 2. within the next four clock cycles, in the same operation, write the wdp bits as desired, but with the wdce bit cleared. the value written to the wde bit is irrelevant. assembly code example (1) wdt_off: ; write logical one to wdce and wde ldi r16, (1< 57 at90can128 4250e?can?12/04 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 311. 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 26 shows reset and interrupt vectors placement for the various combinations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these loca- tions. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: the boot reset address is shown in table 119 on page 323. for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in at90can128 is: ;addresslabels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp ext_int2 ; irq2 handler 0x0008 jmp ext_int3 ; irq3 handler 0x000a jmp ext_int4 ; irq4 handler 0x000c jmp ext_int5 ; irq5 handler 0x000e jmp ext_int6 ; irq6 handler 0x0010 jmp ext_int7 ; irq7 handler 0x0012 jmp tim2_comp ; timer2 compare handler 0x0014 jmp tim2_ovf ; timer2 overflow handler 30 0x003a timer3 compb timer/counter3 compare match b 31 0x003c timer3 compc timer/counter3 compare match c 32 0x003e timer3 ovf timer/counter3 overflow 33 0x0040 usart1, rx usart1, rx complete 34 0x0042 usart1, udre usart1 data register empty 35 0x0044 usart1, tx usart1, tx complete 36 0x0046 twi two-wire serial interface 37 0x0048 spm ready store program memory ready table 26. reset and interrupt vectors placement (note:) bootrst ivsel reset address interrupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 table 25. reset and interrupt vectors (continued) vector no. program address (2) source interrupt definition 58 at90can128 4250e?can?12/04 0x0016 jmp tim1_capt ; timer1 capture handler 0x0018 jmp tim1_compa ; timer1 comparea handler 0x001a jmp tim1_compb ; timer1 compareb handler 0x001c jmp tim1_ovf ; timer1 comparec handler 0x001e jmp tim1_ovf ; timer1 overflow handler 0x0020 jmp tim0_comp ; timer0 compare handler 0x0022 jmp tim0_ovf ; timer0 overflow handler 0x0024 jmp can_it ; can handler 0x0026 jmp ctim_ovf ; can timer overflow handler 0x0028 jmp spi_stc ; spi transfer complete handler 0x002a jmp usart0_rxc ; usart0 rx complete handler 0x002c jmp usart0_dre ; usart0,udr empty handler 0x002e jmp usart0_txc ; usart0 tx complete handler 0x0030 jmp ana_comp ; analog comparator handler 0x0032 jmp adc ; adc conversion complete handler 0x0034 jmp ee_rdy ; eeprom ready handler 0x0036 jmp tim3_capt ; timer3 capture handler 0x0038 jmp tim3_compa ; timer3 comparea handler 0x003a jmp tim3_compb ; timer3 compareb handler 0x003c jmp tim3_compc ; timer3 comparec handler 0x003e jmp tim3_ovf ; timer3 overflow handler 0x0040 jmp usart1_rxc ; usart1 rx complete handler 0x0042 jmp usart1_dre ; usart1,udr empty handler 0x0044 jmp usart1_txc ; usart1 tx complete handler 0x0046 jmp twi ; twi interrupt handler 0x0048 jmp spm_rdy ; spm ready handler ; 0x0049 reset: ldi r16, high(ramend); main program start 0x004a out sph,r16 ;set stack pointer to top of ram 0x004b ldi r16, low(ramend) 0x004c out spl,r16 0x004d sei ; enable interrupts 0x004e 59 at90can128 4250e?can?12/04 ... ... ... ; 0xf00c jmp spm_rdy ; store program memory ready handler when the bootrst fuse is programmed and the boot section size set to 8k bytes, the most typical and general program setup for the reset and interrupt vector addresses is: ;address labels code comments .org 0x0002 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp pcint0 ; pcint0 handler ... ... ... ; 0x002c jmp spm_rdy ; store program memory ready handler ; .org 0xf000 0xf000 reset: ldi r16,high(ramend) ; main program start 0xf001 out sph,r16 ; set stack pointer to top of ram 0xf002 ldi r16,low(ramend) 0xf003 out spl,r16 0xf004 sei ; enable interrupts 0xf005 60 at90can128 4250e?can?12/04 bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. when this bit is set (one), the interrupt vectors are moved to the begin- ning of the boot loader section of the flash. the actual address of the start of the boot flash section is determined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self-programming? on page 311 for details. to avoid unin- tentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: 1. write the interrupt vector change enable (ivce) bit to one. 2. within four cycles, write the desired value to ivsel while writing a zero to ivce. interrupts will automatically be disabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabled until after the instruction fol- lowing the write to ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing from the application section. if interrupt vectors are placed in the application section and boot lock bit blb12 is pro- gramed, interrupts are disabled while executing from the boot loader section. refer to the section ?boot loader support ? read-while-write self-programming? on page 311 for details on boot lock bits. bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is wr itten or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description above. see code example below. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 62 at90can128 4250e?can?12/04 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 31 shows a functional description of one i/o-port pin, here generically called pxn. figure 31. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o-ports? on page 85, the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is config- ured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 63 at90can128 4250e?can?12/04 if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an out- put pin, the port pin is driven low (zero). toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 27 summarizes the control signals for the pin value. reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 31, the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 32 shows a timing diagram of the synchroni zation when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 27. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 64 at90can128 4250e?can?12/04 figure 32. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the suc- ceeding positive clock edge. as indicated by the two arrows t pd,max and t pd,min , a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 33. the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay t pd through the synchronizer is 1 system clock period. figure 33. synchronization when reading a software assigned pin value xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 65 at90can128 4250e?can?12/04 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. digital input enable and sleep modes as shown in figure 31, the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrupt pins. if the external inter- rupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in ?alternate port func- tions? on page 67. if a logic high level (?one?) is present on an asynchronous external interrupt pin config- ured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 67 at90can128 4250e?can?12/04 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 34 shows how the port pin control signals from the simplified figure 31 can be overrid- den by alternate functions. the overriding signals may not be present in all port pins, but the figure serves as a generic description app licable to all port pins in the avr micro- controller family. figure 34. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. table 28 summarizes the function of the overriding signals. the pin and port indexes from figure 34 are not shown in the succeeding tables. the overriding signals are gen- erated internally in the modules having the alternate function. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data b u s 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn wpx ptoexn: pxn, port toggle override enable wpx: write pinx 68 at90can128 4250e?can?12/04 the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternat e function. refer to the alternate function description for further details. mcu control register ? mcucr table 28. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. bit 7 6 5 4 3 2 1 0 jtd ? ?pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 69 at90can128 4250e?can?12/04 bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? for more details about this feature. alternate functions of port a the port a has an alternate function as the address low byte and data lines for the external memory interface. the port a pins with alternate functions are shown in table 29. the alternate pin configuration is as follows: ad7 ? port a, bit 7 ad7, external memory interface address 7 and data 7. ad6 ? port a, bit 6 ad6, external memory interface address 6 and data 6. ad5 ? port a, bit 5 ad5, external memory interface address 5 and data 5. ad4 ? port a, bit 4 ad4, external memory interface address 4 and data 4. ad3 ? port a, bit 3 ad3, external memory interface address 3 and data 3. ad2 ? port a, bit 2 ad2, external memory interface address 2 and data 2. ad1 ? port a, bit 1 ad1, external memory interface address 1 and data 1. ad0 ? port a, bit 0 ad0, external memory interface address 0 and data 0. table 29. port a pins alternate functions port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0) 70 at90can128 4250e?can?12/04 table 30 and table 31 relates the alternate functions of port a to the overriding signals shown in figure 34 on page 67. note: 1. ada is short for address active and represents the time when address is output. see ?external memory interface? on page 24 for details. note: 1. ada is short for address active and represents the time when address is output. see ?external memory interface? on page 24 for details. table 30. overriding signals for alternate functions in pa7..pa4 signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre (ada + wr ) sre (ada + wr ) sre (ada + wr ) sre (ada + wr ) puov0000 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a7 ada + d7 output wr a6 ada + d6 output wr a5 ada + d5 output wr a4 ada + d4 output wr ptoe0000 dieoe 0 0 0 0 dieov 0 0 0 0 di d7 input d6 input d5 input d4 input aio ???? table 31. overriding signals for alternate functions in pa3..pa0 signal name pa3/ad3 pa2/ad2 pa1/ad1 pa0/ad0 puoe sre (ada + wr ) sre (ada + wr ) sre (ada + wr ) sre (ada + wr ) puov0000 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a3 ada + d3 output wr a2 ada + d2 output wr a1 ada + d1 output wr a0 ada + d0 output wr ptoe0000 dieoe0000 dieov0000 di d3 input d2 input d1 input d0 input aio ???? 71 at90can128 4250e?can?12/04 alternate functions of port b the port b pins with alternate functions are shown in table 32. the alternate pin configuration is as follows: oc0a/oc1c, bit 7 oc0a, output compare match a output. the pb7 pin can serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. oc1c, output compare match c output. the pb7 pin can serve as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc1c pin is also the output pin for the pwm mode timer function. oc1b, bit 6 oc1b, output compare match b output. the pb6 pin can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set ?one?) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. oc1a, bit 5 oc1a, output compare match a output. the pb5 pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set ?one?) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. oc2a, bit 4 oc2a, output compare match a output. the pb4 pin can serve as an external output for the timer/counter2 output compare a. the pin has to be configured as an output (ddb4 set ?one?) to serve this function. the oc2a pin is also the output pin for the pwm mode timer function. miso ? port b, bit 3 miso, master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb3. when the spi is enabled as a slave, the data direction of this pin is controlled by table 32. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c (output compare and pwm output a for timer/counter0 or output compare and pwm output c for timer/counter1) pb6 oc1b (output compare and pwm output b for timer/counter1) pb5 oc1a (output compare and pwm output a for timer/counter1) pb4 oc2a (output compare and pwm output a for timer/counter2 ) pb3 miso (spi bus master input/slave output) pb2 mosi (spi bus master output/slave input) pb1 sck (spi bus serial clock) pb0 ss (spi slave select input) 72 at90can128 4250e?can?12/04 ddb3. when the pin is forced to be an input, the pull-up can still be controlled by the portb3 bit. mosi ? port b, bit 2 mosi, spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb2. when the spi is enabled as a master, the data direction of this pin is controlled by ddb2. when the pin is forced to be an input, the pull-up can still be controlled by the portb2 bit. sck ? port b, bit 1 sck, master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1. when the spi is enabled as a master, the data direction of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up can still be controlled by the portb1 bit. ss ? port b, bit 0 ss , slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb0. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be con- trolled by the portb0 bit. table 33 and table 34 relate the alternate fu nctions of port b to the overriding signals shown in figure 34 on page 67. spi mstr input and spi slave output constitute the miso signal, while mosi is divided into spi mstr output and spi slave input. table 33 and table 34 relates the alternate functions of port b to the overriding signals shown in figure 34 on page 67. note: 1. see ?output compare modulator - ocm? on page 160 for details. table 33. overriding signals for alternate functions in pb7..pb4 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puoe0 000 puov0 000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0a/oc1c enable (1) oc1b enable oc1a enable oc2a enable pvov oc0a/oc1c (1) oc1b oc1a oc2a ptoe0 000 dieoe0 000 dieov0 000 di ? ??? aio ? ??? 73 at90can128 4250e?can?12/04 alternate functions of port c the port c has an alternate function as the address high byte for the external memory interface. the port c pins with alternate functions are shown in table 35. the alternate pin configuration is as follows: a15/clko ? port c, bit 7 a15, external memory interface address 15. clko, divided system clock: the divided system clock can be output on the pc7 pin. the divided system clock will be output if the ckout fuse is programmed, regardless of the portc7 and ddc7 settings. it will also be output during reset. table 34. overriding signals for alternate functions in pb3..pb0 signal name pb3/miso pb2/mosi pb1/sck pb0/ss puoe spe mstr spe mstr spe mstr spe mstr puov portb3 pud portb2 pud portb1 pud portb0 pud ddoe spe mstr spe mstr spe mstr spe mstr ddov0000 pvoe spe mstr spe mstr spe mstr 0 pvov spi slave output spi master output sck output 0 ptoe0000 dieoe0000 dieov0000 di spi master input spi slave input reset sck input spi ss aio ???? table 35. port c pins alternate functions port pin alternate function pc7 a15/clko (external memory interface address 15 or divided system clock) pc6 a14 (external memory interface address 14) pc5 a13 (external memory interface address 13) pc4 a12 (external memory interface address 12) pc3 a11 (external memory interface address 11) pc2 a10 (external memory interface address 10) pc1 a9 (external memory interface address 9) pc0 a8 (external memory interface address 8) 74 at90can128 4250e?can?12/04 a14 ? port c, bit 6 a14, external memory interface address 14. a13 ? port c, bit 5 a13, external memory interface address 13. a12 ? port c, bit 4 a12, external memory interface address 12. a11 ? port c, bit 3 a11, external memory interface address 11. a10 ? port c, bit 2 a10, external memory interface address 10. a9 ? port c, bit 1 a9, external memory interface address 9. a8 ? port c, bit 0 a8, external memory interface address 8. table 36 and table 37 relate the alternate functions of port c to the overriding signals shown in figure 34 on page 67. note: 1. ckout is one if the ckout fuse is programmed table 36. overriding signals for alternate functions in pc7..pc4 signal name pc7/a15 pc6/a14 pc5/a13 pc4/a12 puoe sre (xmm < 1) sre (xmm < 2) sre (xmm < 3) sre (xmm < 4) puov0 000 ddoe ckout (1) + (sre (xmm < 1)) sre (xmm < 2) sre (xmm < 3) sre (xmm < 4) ddov 1 1 1 1 pvoe ckout (1) + (sre (xmm < 1)) sre (xmm < 2) sre (xmm < 3) sre (xmm < 4) pvov (a15 ckout (1) ) + (clko ckout (1) ) a14 a13 a12 ptoe0 000 dieoe0 000 dieov0 000 di ? ??? aio ? ??? 75 at90can128 4250e?can?12/04 alternate functions of port d the port d pins with alternate functions are shown in table 38. the alternate pin configuration is as follows: t0/clko ? port d, bit 7 t0, timer/counter0 counter source. rxcan/t1 ? port d, bit 6 rxcan, can receive data (data input pin for the can). when the can controller is enabled this pin is configured as an input regardless of the value of ddd6. when the can forces this pin to be an input, the pull-up can still be controlled by the portd6 bit. t1, timer/counter1 counter source. table 37. overriding signals for alternate functions in pc3..pc0 signal name pc3/a11 pc2/a10 pc1/a9 pc0/a8 puoe sre (xmm < 5) sre (xmm < 6) sre (xmm < 7) sre (xmm < 7) puov0000 ddoe sre (xmm < 5) sre (xmm < 6) sre (xmm < 7) sre (xmm < 7) ddov1111 pvoe sre (xmm < 5) sre (xmm < 6) sre (xmm < 7) sre (xmm < 7) pvov a11 a10 a9 a8 ptoe0000 dieoe0000 dieov0000 di ???? aio ???? table 38. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 rxcan/t1 (can receive pin or timer/counter1 clock input) pd5 txcan/xck1 (can transmit pin or usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 int3/txd1 (external interrupt3 input or uart1 transmit pin) pd2 int2/rxd1 (external interrupt2 input or uart1 receive pin) pd1 int1/sda (external interrupt1 input or twi serial data) pd0 int0/scl (external interrupt0 input or twi serial clock) 76 at90can128 4250e?can?12/04 txcan/xck1 ? port d, bit 5 txcan, can transmit data (data output pin for the can). when the can is enabled, this pin is configured as an output regardless of the value of ddd5. xck1, usart1 external clock. the data direction register (ddd5) controls whether the clock is output (ddd5 set) or input ( ddd45 cleared). the xck1 pin is active only when the usart1 operates in synchronous mode. icp1 ? port d, bit 4 icp1, input capture pin1. the pd4 pin can act as an input capture pin for timer/counter1. int3/txd1 ? port d, bit 3 int3, external interrupt source 3. the pd3 pin can serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1). when the usart1 transmitter is enabled, this pin is configured as an output regardless of the value of ddd3. int2/rxd1 ? port d, bit 2 int2, external interrupt source 2. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the usart1). when the usart1 receiver is enabled this pin is configured as an input regardless of the value of ddd2. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. int1/sda ? port d, bit 1 int1, external interrupt source 1. the pd1 pin can serve as an external interrupt source to the mcu. sda, two-wire serial interface data. when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd1 is disconnected from the port and becomes the serial data i/o pin for the two-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. int0/scl ? port d, bit 0 int0, external interrupt source 0. the pd0 pin can serve as an external interrupt source to the mcu. scl, two-wire serial interface clock: when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd0 is disconnected from the port and becomes the serial clock i/o pin for the two-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. 77 at90can128 4250e?can?12/04 table 39 and table 40 relates the alternate functions of port d to the overriding signals shown in figure 34 on page 67. note: 1. when enabled, the two-wire serial interface enables slew-rate controls on the out- put pins pd0 and pd1. this is not shown in this table. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. table 39. overriding signals for alternate functions pd7..pd4 signal name pd7/t0 pd6/t1/r xcan pd5/xck1/txcan pd4/icp1 puoe 0 rxcanen txcanen + 0 puov 0 portd6 pud 00 ddoe 0 rxcanen txcanen 0 ddov 0 0 1 0 pvoe 0 0 txcanen + umsel1 0 pvov 0 0 (xck1 output umsel1 txcanen ) + (txcan txcanen) 0 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di t0 input t1 input/rxcan xck1 input icp1 input aio ?? ? ? table 40. overriding signals for alternate functions in pd3..pd0 (1) signal name pd3/int3/txd1 pd2/in t2/rxd1 pd1/int1/sda pd0/int0/scl puoe txen1 rxen1 twen twen puov 0 portd2 pud portd1 pud portd0 pud ddoe txen1 rxen1 0 0 ddov 1 0 0 0 pvoe txen1 0 twen twen pvov txd1 0 sda_out scl_out ptoe 0 0 0 0 dieoe int3 enable int2 enable int1 enable int0 enable dieov int3 enable int2 enable int1 enable int0 enable di int3 input int2 input/rxd1 int1 input int0 input aio ?? sda input scl input 78 at90can128 4250e?can?12/04 alternate functions of port e the port e pins with alternate functions are shown in table 41. the alternate pin configuration is as follows: pcint7/icp3 ? port e, bit 7 int7, external interrupt source 7. the pe7 pin can serve as an external interrupt source. icp3, input capture pin3: the pe7 pin can act as an input capture pin for timer/counter3. int6/t3 ? port e, bit 6 int6, external interrupt source 6. the pe6 pin can serve as an external interrupt source. t3, timer/counter3 counter source. int5/oc3c ? port e, bit 5 int5, external interrupt source 5. the pe5 pin can serve as an external interrupt source. oc3c, output compare match c output. the pe5 pin can serve as an external output for the timer/counter3 output compare c. the pin has to be configured as an output (dde5 set ?one?) to serve this function. the oc3c pin is also the output pin for the pwm mode timer function. int4/oc3b ? port e, bit 4 int4, external interrupt source 4. the pe4 pin can serve as an external interrupt source. oc3b, output compare match b output. the pe4 pin can serve as an external output for the timer/counter3 output compare b. the pin has to be configured as an output (dde4 set (one)) to serve this function. the oc3b pin is also the output pin for the pwm mode timer function. table 41. port e pins alternate functions port pin alternate function pe7 int7/icp3 (external interrupt 7 input or timer/counter3 input capture trigger) pe6 int6/ t3 (external interrupt 6 input or timer/counter3 clock input) pe5 int5/oc3c (external interrupt 5 input or output compare and pwm output c for timer/counter3) pe4 int4/oc3b (external interrupt4 input or output compare and pwm output b for timer/counter3) pe3 ain1/oc3a (analog comparator negative input or output compare and pwm output a for timer/counter3) pe2 ain0/xck0 (analog comparator positive input or usart0 external clock input/output) pe1 pdo/txd0 (programming data output or uart0 transmit pin) pe0 pdi/rxd0 (programming data input or uart0 receive pin) 79 at90can128 4250e?can?12/04 ain1/oc3a ? port e, bit 3 ain1 ? analog comparator negative input. this pin is directly connected to the negative input of the analog comparator. oc3a, output compare match a output. the pe3 pin can serve as an external output for the timer/counter3 output compare a. the pin has to be configured as an output (dde3 set ?one?) to serve this function. the oc3a pin is also the output pin for the pwm mode timer function. ain0/xck0 ? port e, bit 2 ain0 ? analog comparator positive input. this pin is directly connected to the positive input of the analog comparator. xck0, usart0 external clock. the data direction register (dde2) controls whether the clock is output (dde2 set) or input (d de2 cleared). the xck0 pin is active only when the usart0 operates in synchronous mode. pdo/txd0 ? port e, bit 1 pdo, spi serial programming data output. during serial program downloading, this pin is used as data output line for the at90can128. txd0, uart0 transmit pin. pdi/rxd0 ? port e, bit 0 pdi, spi serial programming data input. during serial program downloading, this pin is used as data input line for the at90can128. rxd0, usart0 receive pin. receive data (data input pin for the usart0). when the usart0 receiver is enabled this pin is configured as an input regardless of the value of ddre0. when the usart0 forces this pin to be an input, a logical one in porte0 will turn on the internal pull-up. table 42 and table 43 relates the alternate functions of port e to the overriding signals shown in figure 34 on page 67. table 42. overriding signals for alternate functions pe7..pe4 signal name pe7/int7/icp3 pe6/int6/t3 pe5/int5/oc3c pe4/int4/oc3b puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 oc3c enable oc3b enable pvov 0 0 oc3c oc3b ptoe 0 0 0 0 dieoe int7 enable int6 enable int5 enable int4 enable dieov int7 enable int6 enable int5 enable int4 enable di int7 input /icp3 input int6 input /t3 input int5 input int4 input aio ???? 80 at90can128 4250e?can?12/04 note: 1. ain0d and ain1d is described in ?digital input disable register 1 ? didr1? on page 264. alternate functions of port f the port f has an alternate function as analog input for the adc as shown in table 44. if some port f pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. if the jtag interface is enabled, the pull-up resistors on pins pf7 (tdi), pf5 (tms) and pf4 (tck) will be activated even if a reset occurs. the alternate pin configuration is as follows: tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, input channel 7 . table 43. overriding signals for alternate functions in pe3..pe0 signal name pe3/ain1/oc3a pe2/ain 0/xck0 pe1/pdo/txd0 pe0/pdi/rxd0 puoe 0 0 txen0 rxen0 puov000porte0 pud ddoe 0 0 txen0 rxen0 ddov0010 pvoe oc3a enable umsel0 txen0 0 pvov oc3a xck0 output txd0 0 ptoe0000 dieoe ain1d (1) ain0d (1) 00 dieov0000 di 0 xck0 input ? rxd0 aio ain1 input ain0 input ?? table 44. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag data input) pf6 adc6/tdo (adc input channel 6 or jtag data output) pf5 adc5/tms (adc input channel 5 or jtag mode select) pf4 adc4/tck (adc input channel 4 or jtag clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 81 at90can128 4250e?can?12/04 tdi, jtag test data in. serial input data to be shifted in to the instruction register or data register (scan chains). when the jtag interface is enabled, this pin can not be used as an i/o pin. tck, adc6 ? port f, bit 6 adc6, analog to digital converter, input channel 6 . tdo, jtag test data out. serial output data from instruction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. tms, adc5 ? port f, bit 5 adc5, analog to digital converter, input channel 5 . tms, jtag test mode select. this pin is used for navigating through the tap-controller state machine. when the jtag interface is enabled, this pin can not be used as an i/o pin. tdo, adc4 ? port f, bit 4 adc4, analog to digital converter, input channel 4 . tck, jtag test clock. jtag operation is synchronous to tck. when the jtag inter- face is enabled, this pin can not be used as an i/o pin. adc3 ? port f, bit 3 adc3, analog to digital converter, input channel 3. adc2 ? port f, bit 2 adc2, analog to digital converter, input channel 2. adc1 ? port f, bit 1 adc1, analog to digital converter, input channel 1. adc0 ? port f, bit 0 adc0, analog to digital converter, input channel 0. 82 at90can128 4250e?can?12/04 table 45 and table 46 relates the alternate functions of port f to the overriding signals shown in figure 34 on page 67. table 45. overriding signals for alternate functions in pf7..pf4 signal name pf7/adc7/tdi pf6/ adc6/tdo pf5/adc5/tms pf4/adc4/tck puoe jtagen jtagen jtagen jtagen puov jtagen jtagen jtagen jtagen ddoe jtagen jtagen jtagen jtagen ddov 0 shift_ir + shift_dr 00 pvoe jtagen jtagen jtagen jtagen pvov 0 tdo 0 0 ptoe0000 dieoe jtagen + adc7d jtagen + adc6d jtagen + adc5d jtagen + adc4d dieov jtagen 0 jtagen jtagen di tdi ? tms tck aio adc7 input adc6 input adc5 input adc4 input table 46. overriding signals for alternate functions in pf3..pf0 signal name pf3/adc3 pf2/adc2 pf1/adc1 pf0/adc0 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe0000 dieoe adc3d adc2d adc1d adc0d dieov0000 di ???? aio adc3 input adc2 input adc1 input adc0 input 83 at90can128 4250e?can?12/04 alternate functions of port g the alternate pin configuration is as follows: the alternate pin configuration is as follows: tosc1 ? port g, bit 4 tosc2, timer/counter2 oscillator pin 1. when the as2 bit in assr is set (one) to enable asynchronous clocking of timer/counter2, pin pg4 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. in this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. tosc2 ? port g, bit 3 tosc2, timer/counter2 oscillator pin 2. when the as2 bit in assr is set (one) to enable asynchronous clocking of timer/counter2, pin pg3 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. in this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ale ? port g, bit 2 ale is the external data memory address latch enable signal. rd ? port g, bit 1 rd is the external data memory read control strobe. wr ? port g, bit 0 wr is the external data memory write control strobe. table 47. port g pins alternate functions port pin alternate function pg4 tosc1 (rtc oscillator timer/counter2) pg3 tosc2 (rtc oscillator timer/counter2) pg2 ale (address latch enable to external memory) pg1 rd (read strobe to external memory) pg0 wr (write strobe to external memory) 84 at90can128 4250e?can?12/04 table 47 and table 48 relates the alternate functions of port g to the overriding signals shown in figure 34 on page 67. table 48. overriding signals for alternate function in pg4 signal name---pg4/tosc1 puoe as2 puov 0 ddoe as2 ddov 0 pvoe 0 pvov 0 ptoe 0 dieoe as2 dieov exclk di ? aio t/c2 osc input table 49. overriding signals for alternate functions in pg3:0 signal name pg3/tosc2 pg2/ale pg1/rd pg0/wr puoe as2 exclk sre sre sre puov0 000 ddoe as2 exclk sre sre sre ddov 0 1 1 1 pvoe 0 sre sre sre pvov 0 ale rd wr ptoe0 000 dieoe as2 0 0 0 dieov0 000 di ? ??? aio t/c2 osc output ??? 85 at90can128 4250e?can?12/04 register description for i/o-ports port a data register ? porta port a data direction register ? ddra port a input pins address ? pina port b data register ? portb port b data direction register ? ddrb port b input pins address ? pinb port c data register ? portc port c data direction register ? ddrc bit 76543210 porta7 porta6 porta5 porta4 port a3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pina7 pina6 pina5 pina4 pina 3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb 3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portc7 portc6 portc5 portc4 port c3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 86 at90can128 4250e?can?12/04 port c input pins address ? pinc port d data register ? portd port d data direction register ? ddrd port d input pins address ? pind port e data register ? porte port e data direction register ? ddre port e input pins address ? pine port f data register ? portf port f data direction register ? ddrf bit 76543210 pinc7 pinc6 pinc5 pinc4 pinc 3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 port d3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pind7 pind6 pind5 pind4 pind 3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 porte7 porte6 porte5 porte4 port e3 porte2 porte1 porte0 porte read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 portf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 87 at90can128 4250e?can?12/04 port f input pins address ? pinf port g data register ? portg port g data direction register ? ddrg port g input pins address ? ping bit 76543210 pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? ? ? portg4 portg3 portg2 portg1 portg0 portg read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ? ping4 ping3 ping2 ping1 ping0 ping read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 n/a n/a n/a n/a n/a 88 at90can128 4250e?can?12/04 external interrupts the external interrupts are triggered by the int7:0 pins. observe that, if enabled, the interrupts will trigger even if the int7:0 pins are configured as outputs. this feature pro- vides a way of generating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control registers ? eicra (int3:0) and eicrb (int7:4). when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recognition of falling or rising edge inter- rupts on int7:4 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 34. low level interrupts and the edge interrupt on int3:0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. this makes the mcu less sensitive to noise. the changed level is sampled twice by the watchdog oscillator clock. the period of the watchdog oscillator is 1 s (nominal) at 5.0v and 25 c. the frequency of the watchdog oscillator is volt age dependent as shown in the ?electrical characteristics(1)? on page 355. the mcu w ill wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. the start-up time is defined by the sut fuses as described in ?system clock? on page 34. if the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. the required level must be held long enough for the mcu to complete the wake up to trigger the level interrupt. external interrupt control register a ? eicra bits 7..0 ? isc31, isc30 ? isc01, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 50. edges on int3..int0 are registered asynchronously. pulses on int3:0 pins wider than the minimum pulse width given in table 51 will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. when changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by writing a logical one to its interrupt flag bit (intfn) in the eifr register before the interrupt is re- enabled. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 89 at90can128 4250e?can?12/04 note: 1. n = 3, 2, 1or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. external interrupt control register b ? eicrb bits 7..0 ? isc71, isc70 - isc41, isc40: external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are activated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 52. the value on the int7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock per iod will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. note: 1. n = 7, 6, 5 or 4. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. table 50. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 01reserved 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. table 51. asynchronous external interrupt characteristics symbol parameter condition min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns bit 76543210 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 52. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 10 the falling edge between two samples of intn generates an interrupt request. 11 the rising edge between two samples of intn generates an interrupt request. 90 at90can128 4250e?can?12/04 external interrupt mask register ? eimsk bits 7..0 ? int7 ? int0: external interrupt request 7 - 0 enable when an int7 ? int0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense con- trol bits in the external interrupt control registers ? eicra and eicrb ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activ- ity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. external interrupt flag register ? eifr bits 7..0 ? intf7 - intf0: external interrupt flags 7 - 0 when an edge or logic change on the int7:0 pin triggers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int7:0 in eimsk, are set (one), the mcu will jump to the interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int7:0 are configured as level interrupt. note that when entering sleep mode with the int3:0 interrupts disabled, the input buffers on these pins will be disabled. this may cause a logic change in inter- nal signals which will set the intf3:0 flags. see ?digital input enable and sleep modes? on page 65 for more information. bit 76543210 int7 int6 int5 int4 int3 int2 int1 iint0 eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 91 at90can128 4250e?can?12/04 timer/counter3/1/0 prescalers timer/counter3, timer/counter1 and timer/counter0 share the same prescaler mod- ule, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter3, timer/counter1 and timer/counter0. overview most bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number. internal clock source the timer/counter can be clocked direct ly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter3, timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a pres caler reset will affect the prescaler period for all timer/counters it is connected to. external clock source an external clock source applied to the t3/t1/t0 pin can be used as timer/counter clock (clk t3 /clk t1 /clk t0 ). the t3/t1/t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 35 shows a functional equivalent block diagram of the t3/t1/t0 synchronization and edge detector logic. the registers are clocked at the pos- itive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t3 /clk t1 /clk t0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 35. t3/t1/t0 pin sampling the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t3/t1/t0 pin to the counter is updated. tn_sync (to clock select logi c) edge detector synchronization dq dq le dq tn clk i/o 92 at90can128 4250e?can?12/04 enabling and disabling of the clock input must be done when t3/t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk 94 at90can128 4250e?can?12/04 8-bit timer/counter0 with pwm timer/counter0 is a general purpose, single channel, 8-bit timer/counter module. the main features are: features single channel counter clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) frequency generator external event counter 10-bit clock prescaler overflow and compare match interrupt sources (tov0 and ocf0a) overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a value and so on. a simplified block diagram of the 8-bit timer/counter is shown in figure 37. for the actual placement of i/o pins, refer to ?pinout at90can128- tqfp? on page 4. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device- specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 104. figure 37. 8-bit timer/counter block diagram registers the timer/counter (tcnt0) and output compare register (ocr0a) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all visible in the timer timer/counter data b u s = tcntn waveform generation ocnx = 0 control logic = 0xff bottom count clear direction tovn (int.req.) ocrnx tccrn clock select tn edge detector ( from prescaler ) clk tn top ocn (int.req.) 95 at90can128 4250e?can?12/04 interrupt flag register (tifr0). all interrupts are individually masked with the timer interrupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare register (ocr0a) is compared with the timer/counter value at all times. the result of the compare can be used by the wave- form generator to generate a pwm or variable frequency output on the output compare pin (oc0a). see ?output compare unit? on page 96 for details. the compare match event will also set the compare flag (ocf0a) which can be used to generate an output compare interrupt request. definitions the definitions in table 53 are also used extensively throughout the document. timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0a). for details on clock sources and prescaler, see ?timer/counter3/1/0 prescalers? on page 91. counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 38 shows a block diagram of the counter and its surroundings. figure 38. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). table 53. definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 96 at90can128 4250e?can?12/04 clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has reached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc0a. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 99. the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm01:0 bits. tov0 can be used for generating a cpu interrupt. output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare register (ocr0a). whenever tcnt0 equals ocr0a, the comparator signals a match. a match will set the output compare flag (ocf0a) at the next timer clock cycle. if enabled (ocie0a = 1 and global interrupt flag in sreg is set), the output compare flag gen- erates an output compare interrupt. the ocf0a flag is automatically cleared when the interrupt is executed. alternatively, the ocf0a flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm01:0 bits and com- pare output mode (com0a1:0) bits. t he max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 99 ). figure 39 shows a block diagram of the output compare unit. figure 39. output compare unit, block diagram ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 97 at90can128 4250e?can?12/04 the ocr0a register is double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr0a compare register to either top or bottom of the counting sequence. the syn- chronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0a register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0a buffer register, and if double buffering is disabled the cpu will access the ocr0a directly. force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0a) bit. forcing compare match will not set the ocf0a flag or reload/clear the timer, but the oc0a pin will be updated as if a real compare match had occu rred (the com0a1:0 bits settings define whether the oc0a pin is set, cleared or toggled). compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0a to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tcnt0 in any mode of operat ion will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare channel, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0a should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0a value is to use the force output compare (foc0a) strobe bits in normal mode. the oc0a register keeps its value even when changing between waveform generation modes. be aware that the com0a1:0 bits are not double buffered together with the compare value. changing the com0a1:0 bits will take effect immediately. 98 at90can128 4250e?can?12/04 compare match output unit the compare output mode (com0a1:0) bits have two functions. the waveform gener- ator uses the com0a1:0 bits for defining the output compare (oc0a) state at the next compare match. also, the com0a1:0 bits control the oc0a pin output source. figure 40 shows a simplified schematic of the logic affected by the com0a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0a1:0 bits are shown. when referring to the oc0a state, the reference is for the internal oc0a register, not the oc0a pin. if a system reset occur, the oc0a register is reset to ?0?. figure 40. compare match output unit, schematic compare output function the general i/o port function is overridden by the output compare (oc0a) from the waveform generator if either of the com0a1:0 bits are set. however, the oc0a pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc0a pin (ddr_oc0a) must be set as output before the oc0a value is visible on the pin. the port override function is indepen- dent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0a state before the output is enabled. note that some com0a1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 104 compare output mode and waveform generation the waveform generator uses the com0a1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0a1:0 = 0 tells the waveform generator that no action on the oc0a register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 55 on page 105. for fast pwm mode, refer to table 56 on page 105, and for phase correct pwm refer to table 57 on page 106. a change of the com0a1:0 bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc0a strobe bits. port ddr dq dq ocn x pin ocnx dq waveform generator c omnx1 c omnx0 0 1 data b u s f ocnx clk i/o 99 at90can128 4250e?can?12/04 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm01:0) and compare output mode (com0a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0a1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0a1:0 bits control whether the out- put should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 98 ). for detailed timing information refer to figure 44, figure 45, figure 46 and figure 47 in ?timer/counter timing diagrams? on page 102. normal mode the simplest mode of operation is the normal mode (wgm01:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm01:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 41. the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 41. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written t cntn o cnx ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) 100 at90can128 4250e?can?12/04 to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform fre- quency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. fast pwm mode the fast pulse width modulation or fast pwm mode (wgm01:0 = 3) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc0a) is cleared on the compare match between tcnt0 and ocr0a, and set at bot- tom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual- slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 42. the tcnt0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 42. fast pwm mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag se t 4 5 6 7 101 at90can128 4250e?can?12/04 the timer/counter overflow flag (tov0) is set each time the counter reaches max. if the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com0a1:0 to three (see table 56 on page 105). the actual oc0a value will only be visible on the port pin if the data direc- tion for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0a register at the compare match between ocr0a and tcnt0, and clearing (or setting) the oc0a register at the timer clock cycle the counter is cleared (changes from max to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc0a to toggle its logical level on each compare match (com0a1:0 = 1). the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. phase correct pwm mode the phase correct pwm mode (wgm01:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phas e correct pwm mode is based on a dual- slope operation. the counter counts repeatedly from bottom to max and then from max to bottom. in non-inverting compare output mode, the output compare (oc0a) is cleared on the compare match between tcnt0 and ocr0a while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode is fixed to eight bits. in phase correct pwm mode the counter is incremented until the counter value matches max. when the counter reaches max, it changes the count direction. the tcnt0 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 43. the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes repre- sent compare matches between ocr0a and tcnt0. f ocnxpwm f clk_i/o n 256 ? ------------------ = 102 at90can128 4250e?can?12/04 figure 43. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bot- tom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0a1:0 to three (see table 57 on page 106). the actual oc0a value will only be visible on the port pin if the data direc- tion for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0a register at the compare match between ocr0a and tcnt0 when the counter increments, and setting (or clearing) the oc0a register at compare match between ocr0a and tcnt0 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 44 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 103 at90can128 4250e?can?12/04 figure 44. timer/counter timing diagram, no prescaling figure 45 shows the same timing data, but with the prescaler enabled. figure 45. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 46 shows the setting of ocf0a in all modes except ctc mode. figure 46. timer/counter timing diagram, setting of ocf0a, with prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 104 at90can128 4250e?can?12/04 figure 47 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 47. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) 8-bit timer/counter register description timer/counter0 control register a ? tccr0a bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm00 bit specifies a non-pwm mode. how- ever, for ensuring compatibility with future devices, this bit must be set to zero when tccr0 is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. bit 6, 3 ? wgm01:0: waveform generation mode these bits control the counting sequence of the counter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of oper- ation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes. see table 54 and ?modes of operation? on page 99. ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 tccr0 read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 105 at90can128 4250e?can?12/04 note: 1. the ctc0 and pwm0 bit definition names are now obsolete. use the wgm01:0 def- initions. however, the functionality and location of these bits are compatible with previous versions of the timer. bit 5:4 ? com01:0: compare match output mode these bits control the output compare pi n (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit cor- responding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm01:0 bit setting. table 55 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to a normal or ctc mode (non-pwm). table 56 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 100 for more details. table 54. waveform generation mode bit description (1) mode wgm01 (ctc0) wgm00 (pwm0) timer/counter mode of operation top update of ocr0a at tov0 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 21 0ctc ocr0aimmediatemax 31 1fast pwm 0xfftop max table 55. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 56. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 1 0 clear oc0a on compare match. set oc0a at top 1 1 set oc0a on compare match. clear oc0a at top 106 at90can128 4250e?can?12/04 table 57 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect pwm mode? on page 101 for more details. bit 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. if external pin modes are used for the time r/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. timer/counter0 register ? tcnt0 the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0a register. table 57. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when downcounting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when downcounting. table 58. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 107 at90can128 4250e?can?12/04 output compare register a ? ocr0a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. timer/counter0 interrupt mask register ? timsk0 bit 7..2 ? reserved bits these are reserved bits for future use. bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. timer/counter0 interrupt flag register ? tifr0 bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set (one) when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set (one), the timer/counter0 compare match interrupt is executed. bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. in phase correct pwm mode, this bit is set when timer/counter0 changes counting direction at 0x00. bit 76543210 ocr0a[7:0] ocr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? ? ? ocie0a toie0 timsk0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ??????ocf0a tov0 tifr0 read/write r r r r r r r/w r/w initial value00000000 108 at90can128 4250e?can?12/04 16-bit timer/counter (timer/counter1 and timer/counter3) the 16-bit timer/counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. the main features are: features true 16-bit design (i.e., allows 16-bit pwm) three independent output compare units double buffered output compare registers one input capture unit input capture noise canceler clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) variable pwm period frequency generator external event counter four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1 for timer/counter1 - tov3, ocf3a, ocf3b, and icf3 for timer/counter3) overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 1 or 3. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a lower case ?x? replaces the output compare unit channel, in this case a, b or c. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocrna for accessing timer/countern output compare channel a value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 48. for the actual placement of i/o pins, refer to ?pinout at90can128- tqfp? on page 4. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device- specific i/o register and bit locations are listed in the ?16-bit timer/counter register description? on page 131. 109 at90can128 4250e?can?12/04 figure 48. 16-bit timer/counter block diagram (1) note: 1. refer to figure 2 on page 4, table 32 on page 71, and table 41 on page 78 for timer/counter 1 and 3 pin placement and description. registers the timer/counter (tcntn), output compare registers (ocrnx), and input capture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?access- ing 16-bit registers? on page 111. the timer/counter control registers (tccrnx) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifrn). all interrupts are individually masked with the timer interrupt mask register (timskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is icfn (int.req.) tovn (int.req.) clock select timer/counter databus ocrna ocrnb ocrnc icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn 110 at90can128 4250e?can?12/04 inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrnx) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (ocnx). see ?output compare units? on page 118 . the compare match event will also set the compare match flag (ocfnx) which can be used to generate an output com- pare interrupt request. the input capture register can capture the timer/counter value at a given external (edge triggered) event on either the input capture pin (icpn) or on the analog compar- ator pins (see ?analog comparator? on page 262 ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocrna register, the i crn register, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna register can not be used for generating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. definitions the following definitions are used extensively throughout the section: compatibility the 16-bit timer/counter has been updated and improved from previous versions of the 16-bit avr timer/counter. this 16-bit timer/counter is fully compatible with the earlier version regarding: all 16-bit timer/counter related i/o register address locations, including timer interrupt registers. bit locations inside all 16-bit timer/counter registers, including timer interrupt registers. interrupt vectors. the following control bits have changed name, but have same functionality and register location: pwmn0 is changed to wgmn0. pwmn1 is changed to wgmn1. ctcn is changed to wgmn2. the following registers are added to the 16-bit timer/counter: timer/counter control register c (tccrnc). output compare register c, ocrn ch and ocrncl, combined ocrnc. table 59. definitions bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65,535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr n a or icr n regis- ter. the assignment is dependent of the mode of operation. 111 at90can128 4250e?can?12/04 the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. the following bits are added to the 16-bit timer/counter control registers: comnc1:0 are added to tccrna. focna, focnb and focnc are added to tccrnc. wgmn3 is added to tccrnb. interrupt flag and mask bits for output compare unit c are added. the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. accessing 16-bit registers the tcntn, ocrnx, and icrn are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporar y register for the high byte. reading the ocrnx 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. 112 at90can128 4250e?can?12/04 code examples the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrnx and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. note: 1. the example code assumes that the part specific header file is included. the assembly code example returns the tcntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an inter- rupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by acce ssing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff sts tcntnh,r17 sts tcntnl,r16 ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcnt n = 0x1ff; /* read tcntn into i */ i = tcntn; ... 113 at90can128 4250e?can?12/04 the following code examples show how to do an atomic read of the tcntn register contents. reading any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. assembly code example (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } 114 at90can128 4250e?can?12/04 the following code examples show how to do an atomic write of the tcntn register contents. writing any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcntn. reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 sts tcntnh,r17 sts tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 115 at90can128 4250e?can?12/04 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see ?timer/counter3/1/0 prescalers? on page 91. counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 49 shows a block diagram of the counter and its surroundings. figure 49. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcntnh) containing the upper eight bits of the counter, and counter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirectly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register value when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is impor- tant to notice that there are special cases of writing to the tcntn register when the counter is counting that will give unpredictable results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, independent of whether clk t n is present or not. a cpu write over- rides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs ocnx. for more details temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 116 at90can128 4250e?can?12/04 about advanced counting sequences and waveform generation, see ?modes of opera- tion? on page 121. the timer/counter overflow flag (tovn) is set according to the mode of operation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via the icpn pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequency, duty- cycle, and other features of the signal appl ied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 50. the ele- ments of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 50. input capture unit block diagram note: the analog comparator output (aco) can only trigger the timer/counter1 ic unit? not timer/counter3. when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a capture is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copied write icrn (16-bit register) icrnh (8-bit) temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icf1 (int.req .) noise canceler edge detector acic* icnc1 ices1 icp1 analog comparator aco* icf3 (int.req .) noise canceler icp3 edge detector icnc3 ices3 117 at90can128 4250e?can?12/04 into icrn register. if enabled (icien = 1), the input capture flag generates an input capture interrupt. the icfn flag is automatically cleared when the interrupt is executed. alternatively the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (i crnh). when the low byte is read the high byte is copied into the high byte tempor ary register (temp). when the cpu reads the icrnh i/o location it will access the temp register. the icrn register can only be written when using a waveform generation mode that utilizes the icrn register for defining the counter?s top value. in these cases the waveform generation mode (wgmn3:0) bits must be set before the top value can be written to the icrn register. when writing the icrn register the high byte must be writ- ten to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 111. input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). only timer/counter1 can alternatively use the a nalog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by set- ting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a cap- ture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the analog comparator output (aco) inputs are sampled using the same technique as for the tn pin (figure 35 on page 91). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the nois e canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icrn to define top. an input capture can be triggered by software by controlling the port of the icpn pin. noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler intro- duces additional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the system clock and is there- fore not affected by the prescaler. using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icrn register before the next event occurs, the icrn will be overwritten with a new value. in this case the result of the cap- ture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has rela- tively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 118 at90can128 4250e?can?12/04 using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if an interrupt handler is used). output compare units the 16-bit comparator continuously compares tcntn with the output compare regis- ter (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next timer clock cycle. if enabled (ocienx = 1), the output compare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is executed. alternatively the ocfnx flag can be cleared by software by writing a logical one to its i/o bit location. the waveform gen- erator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 121 ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 51 shows a block diagram of the output compare unit. the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 51. output compare unit, block diagram ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf.(8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf.(8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 119 at90can128 4250e?can?12/04 the ocrnx register is double buffered when using any of the twelve pulse width mod- ulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocrnx compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is disabled the cpu will access the ocrnx directly. the content of the ocrnx (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icrn register). therefore ocrnx is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocrnx registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low byte (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare reg- ister in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 111. force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forcing compare match will not set the ocfnx flag or reload/ clear the timer, but the ocnx pin will be updated as if a real compare match had occurred (the comnx1:0 bits settings define whether the ocnx pin is set, cleared or toggled). compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tcntn without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tcntn in any mode of operat ion will block all compare matches for one timer clock cycle, there are risks involved when changing tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the compare match will be missed, resulting in incorrect waveform generation. do not write the tcntn equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. similarly, do not write the tcntn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output compare (focnx) strobe bits in normal mode. the ocnx register keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not double buffered together with the compare value. changing the comnx1:0 bits will take effect immediately. 120 at90can128 4250e?can?12/04 compare match output unit the compare output mode (comnx1:0) bits have two functions. the waveform gener- ator uses the comnx1:0 bits for defining the output compare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. fig- ure 52 shows a simplified schematic of the l ogic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. when referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. figure 52. compare match output unit, schematic compare output function the general i/o port function is overridden by the output compare (ocnx) from the waveform generator if either of the comnx1:0 bits are set. however, the ocnx pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be set as output before the ocnx value is visible on the pin. the port override function is generally independent of the waveform generation mode, but there are some exceptions. refer to table 60, table 61 and table 62 for details. the design of the output compare pin logic allows initialization of the ocnx state before the output is enabled. note that some comnx1:0 bit settings are reserved for certain modes of operation. see ?16-bit timer/counter register description? on page 131 the comnx1:0 bits have no effect on the input capture unit. port ddr dq dq ocn x pin ocnx dq waveform generator c omnx1 c omnx0 0 1 data b u s f ocnx clk i/o 121 at90can128 4250e?can?12/04 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the waveform generator that no action on the ocnx register is to be performed on the next compare match. for com- pare output actions in the non-pwm modes refer to table 60 on page 131. for fast pwm mode refer to table 61 on page 132, and for phase correct and phase and fre- quency correct pwm refer to table 62 on page 132. a change of the comnx1:0 bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the focnx strobe bits. modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the comnx1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the out- put should be set, cleared or toggle at a compare match (see ?compare match output unit? on page 120 ) for detailed timing information refer to ?timer/counter timing diagrams? on page 128. normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter over- flow flag (tovn) will be set in the same timer clock cycle as the tcntn becomes zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maxi- mum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 53. the counter value (tcntn) increases until a compare match occurs with either ocrna or icrn, and then counter (tcntn) is cleared. 122 at90can128 4250e?can?12/04 figure 53. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the com- pare match. the counter will then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocrna then will be double buffered. for generating a waveform output in ctc mode, the ocna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) pro- vides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compare match between tcntn and ocrnx, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high fre- quency allows physically small sized exte rnal components (coils, capacitors), hence reduces total system cost. t cntn o cna ( toggle) ocna interrupt flag set or icfn interrupt flag se t (interrupt on top) 1 4 p eriod 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = 123 at90can128 4250e?can?12/04 the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 54. the figure shows fast pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illus- trating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a com- pare match occurs. figure 54. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer clock cycle as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a co mpare match will never occur between the tcntn and the ocrnx. note that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icrn value written is lower than the current value of tcntn. the result will then be that the counter will miss the compare match at the top value. r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 124 at90can128 4250e?can?12/04 the counter will then have to count to the max value (0xffff) and wrap around start- ing at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare regi ster will then be updated with the value in the buffer register at the next timer clock cycle the tcntn matches top. the update is done at the same timer clock cycle as the tcntn is cleared and the tovn flag is set. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively changed (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 132). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by set- ting (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocrnx equal to top will result in a constant high or low output (depending on the polar- ity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting ocna to toggle its logical level on each compare match (comna1:0 = 1). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = 125 at90can128 4250e?can?12/04 ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 55. the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes repre- sent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 55. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches bot- tom. when either ocrna or icrn is used for defining the top value, the ocna or icfn flag is set accordingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interrupt flags can be used to gener- ate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a co mpare match will never occur between the tcntn and the ocrnx. note that when using fixed top values, the unused bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 55 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx register. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of the fall- r pcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2 ) (comnx1:0 = 3 ) 126 at90can128 4250e?can?12/04 ing slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 132). the actual ocnx value will only be visible on the port pin if the data direc- tion for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the fol- lowing equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency cor- rect pwm mode (wgmn3:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bot- tom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation frequency com- pared to the single-slope operation. however, due to the symmetric feature of the dual- slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is updated by the ocrnx buffer register, (see figure 55 and figure 56). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated using the following equation: f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 127 at90can128 4250e?can?12/04 in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the count direc- tion. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 56. the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a com- pare match occurs. figure 56. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a co mpare match will never occur between the tcntn and the ocrnx. as figure 56 shows the output generated is, in contrast to the phase correct mode, sym- metrical in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will al ways be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively changed by changing the top value, using the ocrna as top is clearly a better choice due to its double buffer feature. ocrnx/top update and tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 128 at90can128 4250e?can?12/04 in phase and frequency correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 132). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter increments, and clearing (or set- ting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequency for the output when using phase and fre- quency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocrnx register is updated with the ocrnx buffer value (only for modes utilizing double buffering). figure 57 shows a timing diagram for the setting of ocfnx. figure 57. timer/counter timing diagram, setting of ocfnx, no prescaling figure 58 shows the same timing data, but with the prescaler enabled. f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = clk tn (clk i/o /1) o cfnx clk i/o o crnx t cntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 129 at90can128 4250e?can?12/04 figure 58. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 59 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. figure 59. timer/counter timing diagram, no prescaling figure 60 shows the same timing data, but with the prescaler enabled. o cfnx o crnx t cntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn ( pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o 130 at90can128 4250e?can?12/04 figure 60. timer/counter timing diagram, with prescaler (f clk_i/o /8) tovn (fpwm) a nd icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 131 at90can128 4250e?can?12/04 16-bit timer/counter register description timer/counter1 control register a ? tccr1a timer/counter3 control register a ? tccr3a bit 7:6 ? comna1:0: compare output mode for channel a bit 5:4 ? comnb1:0: compare output mode for channel b bit 3:2 ? comnc1:0: compare output mode for channel c the comna1:0, comnb1:0 and comnc1:0 control the output compare pins (ocna, ocnb and ocnc respectively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overrides the normal port functionality of the i/o pin it is con- nected to. if one or both of the comnb1:0 bit are written to one, the ocnb output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnc1:0 bit are written to one, the ocnc output overrides the normal port func- tionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output driver. when the ocna, ocnb or ocnc is connected to the pin, the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 60 shows the comnx1:0 bit func- tionality when the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). bit 7 6 5 4 3210 com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3210 com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 tccr3a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 60. compare output mode, non-pwm comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 toggle ocna/ocnb/ocnc on compare match. 1 0 clear ocna/ocnb/ocnc on compare match (set output to low level). 1 1 set ocna/ocnb/ocnc on compare match (set output to high level). 132 at90can128 4250e?can?12/04 table 61 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 122 for more details. table 62 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocna/ocnb/ocnc equals top and comna1/comnb1/comnc1 is set. see ?phase correct pwm mode? on page 124 for more details. bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be us ed, see table 63. modes of operation sup- ported by the timer/counter unit are: normal mode (counter), clear timer on compare table 61. compare output mode, fast pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 1 0 clear ocna/ocnb/ocnc on compare match set ocna/ocnb/ocnc at top 1 1 set ocna/ocnb/ocnc on compare match clear ocna/ocnb/ocnc at top table 62. compare output mode, phase correct and phase and frequency correct pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 1 0 clear ocna/ocnb/ocnc on compare match when up-counting. set ocna/ocnb/ocnc on compare match when downcounting. 1 1 set ocna/ocnb/ocnc on compare match when up-counting. clear ocna/ocnb/ocnc on compare match when downcounting. 133 at90can128 4250e?can?12/04 match (ctc) mode, and three types of pulse width modulation (pwm) modes. (see ?modes of operation? on page 121 ). note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. timer/counter1 control register b ? tccr1b timer/counter3 control register b ? tccr3b bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise can- celer is activated, the input from the input capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. table 63. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrnx at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10- bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 8 1 0 0 0 pwm, phase and frequency correct icrn bottom bottom 9 1 0 0 1 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn top top 15 1 1 1 1 fast pwm ocrna top top bit 7654 3210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7654 3210 icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 134 at90can128 4250e?can?12/04 bit 6 ? icesn: input capture edge select this bit selects which edge on the input capture pin (icpn) that is used to trigger a cap- ture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will also set the input capture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequently the input capture function is disabled. bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future devices, this bit must be written to zero when tccrnb is written. bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 57 and figure 58. if external pin modes are used for the time r/countern, transitions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. timer/counter1 control register c ? tccr1c table 64. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654 3210 foc1a foc1b foc1c ? ? ? ? ? tccr1c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 135 at90can128 4250e?can?12/04 timer/counter3 control register c ? tccr3c bit 7 ? focna: force output compare for channel a bit 6 ? focnb: force output compare for channel b bit 5 ? focnc: force output compare for channel c the focna/focnb/focnc bits are only active when the wgmn3:0 bits specifies a non-pwm mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccrna is written when operating in a pwm mode. when writing a logical one to the focna/focnb/focnc bit, an immediate compare match is forced on the waveform generation unit. the ocna/ocnb/ocnc output is changed according to its comnx1:0 bits setting. note that the focna/focnb/focnc bits are implemented as strobes. therefore it is t he value present in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb/focnc strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb/focnc bits are always read as zero. timer/counter1 ? tcnt1h and tcnt1l timer/counter3 ? tcnt3h and tcnt3l the two timer/counter i/o locations (tcntnh and tcntnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit tempo- rary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111 modifying the counter (tcntn) while the counter is running introduces a risk of missing a compare match between tcntn and one of the ocrnx registers. writing to the tcntn register blocks (removes) the compare match on the following timer clock for all compare units. bit 7654 3210 foc3a foc3b foc3c ? ? ? ? ? tccr3c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 tcnt3[15:8] tcnt3h tcnt3[7:0] tcnt3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 136 at90can128 4250e?can?12/04 output compare register a ? ocr1ah and ocr1al output compare register b ? ocr1bh and ocr1bl output compare register c ? ocr1ch and ocr1cl output compare register a ? ocr3ah and ocr3al output compare register b ? ocr3bh and ocr3bl output compare register c ? ocr3ch and ocr3cl the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcntn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111 input capture register ? icr1h and icr1l bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1c[15:8] ocr1ch ocr1c[7:0] ocr1cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3a[15:8] ocr3ah ocr3a[7:0] ocr3al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3b[15:8] ocr3bh ocr3b[7:0] ocr3bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3c[15:8] ocr3ch ocr3c[7:0] ocr3cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w 137 at90can128 4250e?can?12/04 input capture register ? icr3h and icr3l the input capture is updated with the counter (tcntn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is per- formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111 timer/counter1 interrupt mask register ? timsk1 timer/counter3 interrupt mask register ? timsk3 bit 7..6 ? reserved bits these bits are reserved for future use. bit 5 ? icien: input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 56 ) is executed when the icfn flag, located in tifrn, is set. bit 4 ? reserved bit this bit is reserved for future use. bit 3 ? ocienc: output compare c match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 56 ) is executed when the ocfnc flag, located in tifrn, is set. bit 2 ? ocienb: output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 56 ) is executed when the ocfnb flag, located in tifrn, is set. initial value00000000 bit 76543210 icr3[15:8] icr3h icr3[7:0] icr3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 765432 10 ? ? icie1 ? ocie1c ocie1b ocie1a toie1 timsk1 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 765432 10 ? ? icie3 ? ocie3c ocie3b ocie3a toie3 timsk3 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 138 at90can128 4250e?can?12/04 bit 1 ? ociena: output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 56 ) is executed when the ocfna flag, located in tifrn, is set. bit 0 ? toien: timer/counter overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern overflow interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 56 ) is executed when the tovn flag, located in tifrn, is set. timer/counter1 interrupt flag register ? tifr1 timer/counter3 interrupt flag register ? tifr3 bit 7..6 ? reserved bits these bits are reserved for future use. bit 5 ? icfn: input capture flag this flag is set when a capture event occurs on the icpn pin. when the input capture register (icrn) is set by the wgmn3:0 to be used as the top value, the icfn flag is set when the counter reaches the top value. icfn is automatically cleared when the input capture interrupt vector is executed. alter- natively, icfn can be cleared by writing a logic one to its bit location. bit 4 ? reserved bit this bit is reserved for future use. bit 3 ? ocfnc: output compare c match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the out- put compare register c (ocrnc). note that a forced output compare (focnc) strobe will not set the ocfnc flag. ocfnc is automatically cleared when the output compare match c interrupt vector is executed. alternatively, ocfnc can be cleared by writing a logic one to its bit location. bit 2 ? ocfnb: output compare b match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the out- put compare register b (ocrnb). note that a forced output compare (focnb) strobe will not set the ocfnb flag. bit 76543210 ? ? icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/write r r r/w r r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/write r r r/w r r/w r/w r/w r/w initial value00000000 139 at90can128 4250e?can?12/04 ocfnb is automatically cleared when the output compare match b interrupt vector is executed. alternatively, ocfnb can be cleared by writing a logic one to its bit location. bit 1 ? ocfna: output compare a match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the out- put compare register a (ocrna). note that a forced output compare (focna) strobe will not set the ocfna flag. ocfna is automatically cleared when the output compare match a interrupt vector is executed. alternatively, ocfna can be cleared by writing a logic one to its bit location. bit 0 ? tovn: timer/counter overflow flag the setting of this flag is dependent of the wgmn3:0 bits setting. in normal and ctc modes, the tovn flag is set when the timer overflows. refer to table 63 on page 133 for the tovn flag behavior when using another wgmn3:0 bit setting. tovn is automatically cleared when the timer/countern overflow interrupt vector is executed. alternatively, tovn can be cleared by writing a logic one to its bit location. 140 at90can128 4250e?can?12/04 8-bit timer/counter2 with pwm and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: features single channel counter clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) frequency generator 10-bit clock prescaler overflow and compare match interrupt sources (tov2 and ocf2a) allows clocking from external 32 khz watch crystal independent of the i/o clock overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr2a for accessing timer/counter2 output compare channel a value and so on. a simplified block diagram of the 8-bit timer/counter is shown in figure 61. for the actual placement of i/o pins, refer to figure 2 on page 4. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 151. 141 at90can128 4250e?can?12/04 figure 61. 8-bit timer/counter2 block diagram the timer/counter (tcnt2) and output compare register (ocr2a) are 8-bit registers. interrupt request (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked interna lly, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block controls which clock source the timer/counter uses to increment (or decre- ment) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a) is compared with the timer/counter value at all times. the result of the compare can be used by the wave- form generator to generate a pwm or variable frequency output on the output compare pin (oc2a). see ?output compare unit? on page 143 for details. the compare match event will also set the compare flag (ocf2a) which can be used to generate an output compare interrupt request. definitions the definitions in table 65 are also used extensively throughout the section. timer/counter data b u s = tcntn waveform generation ocnx = 0 control logic = 0xff top bottom count clear direction tovn (int.req.) ocnx (int.req.) synchronization unit ocrnx tccrnx assrn status flags clk i/o clk asy synchronized status flags asynchronous mode select (asn) tosc 2 t/c oscillator tosc 1 prescaler clk tn clk i/o 142 at90can128 4250e?can?12/04 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchro- nous clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs22:0) bits located in the timer/counter control register (tccr2).the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2 or directly from tosc1. for details on asynchronous operation, see ?asynchronous status register ? assr? on page 154. for details on clock sources and prescaler, see ?timer/counter2 prescaler? on page 158. counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 62 shows a block diagram of the counter and its surrounding environment. figure 62. counter unit block diagram figure 63. signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk t 2 timer/counter clock. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). when no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed table 65. definitions bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc2 t/c oscillator tosc1 prescaler clk i/o clk tn clk tns 143 at90can128 4250e?can?12/04 by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc2a. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 145. the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the wgm21:0 bits. tov2 can be used for generating a cpu interrupt. output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a). whenever tcnt2 equals ocr2a, the comparator signals a match. a match will set the output compare flag (ocf2a) at the next timer clock cycle. if enabled (ocie2a = 1), the output compare flag generates an output compare interrupt. the ocf2a flag is automatically cleared when the interrupt is executed. alternatively, the ocf2a flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operat- ing mode set by the wgm21:0 bits and compare output mode (com2a1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (?modes of operation? on page 145). figure 64 shows a block diagram of the output compare unit. figure 64. output compare unit, block diagram the ocr2a register is double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2a compare register to either top or bottom of the counting sequence. the syn- chronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2a register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr2a buffer register, and if double buffering is disabled the cpu will access the ocr2a directly. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 144 at90can128 4250e?can?12/04 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc2a) bit. forcing compare match will not set the ocf2a flag or reload/clear the timer, but the oc2a pin will be updated as if a real compare match had occu rred (the com2a1:0 bits settings define whether the oc2a pin is set, cleared or toggled). compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2a to be initialized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tcnt2 in any mode of operat ion will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the timer/counter is running or not. if the value written to tcnt2 equals the ocr2a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2a should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2a value is to use the force output compare (foc2a) strobe bit in normal mode. the oc2a register keeps its value even when changing between waveform generation modes. be aware that the com2a1:0 bits are not double buffered together with the compare value. changing the com2a1:0 bits will take effect immediately. 145 at90can128 4250e?can?12/04 compare match output unit the compare output mode (com2a1:0) bits have two functions. the waveform gener- ator uses the com2a1:0 bits for defining the output compare (oc2a) state at the next compare match. also, the com2a1:0 bits control the oc2a pin output source. figure 65 shows a simplified schematic of the logic affected by the com2a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2a1:0 bits are shown. when referring to the oc2a state, the reference is for the internal oc2a register, not the oc2a pin. figure 65. compare match output unit, schematic compare output function the general i/o port function is overridden by the output compare (oc2a) from the waveform generator if either of the com2a1:0 bits are set. however, the oc2a pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc2a pin (ddr_oc2a) must be set as output before the oc2a value is visible on the pin. the port override function is indepen- dent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc2a state before the output is enabled. note that some com2a1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 151 compare output mode and waveform generation the waveform generator uses the com2a1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2a1:0 = 0 tells the waveform generator that no action on the oc2a register is to be performed on the next compare match. for com- pare output actions in the non-pwm modes refer to table 67 on page 152. for fast pwm mode, refer to table 68 on page 152, and for phase correct pwm refer to table 69 on page 153. a change of the com2a1:0 bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc2a strobe bits. modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm21:0) and port ddr dq dq ocn x pin ocnx dq waveform generator c omnx1 c omnx0 0 1 data b u s f ocnx clk i/o 146 at90can128 4250e?can?12/04 compare output mode (com2a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2a1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com2a1:0 bits control whether the out- put should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 145 ). for detailed timing information refer to ?timer/counter timing diagrams? on page 150. normal mode the simplest mode of operation is the normal mode (wgm21:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm21:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 66. the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2a, and then counter (tcnt2) is cleared. figure 66. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bot- tom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. t cntn o cnx ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) 147 at90can128 4250e?can?12/04 for generating a waveform output in ctc mode, the oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform fre- quency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. fast pwm mode the fast pulse width modulation or fast pwm mode (wgm21:0 = 3) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc2a) is cleared on the compare match between tcnt2 and ocr2a, and set at bot- tom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that uses dual- slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 67. the tcnt2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. figure 67. fast pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches max. if the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag se t 4 5 6 7 148 at90can128 4250e?can?12/04 in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2a pin. setting the com2a1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com2a1:0 to three (see table 68 on page 152). the actual oc2a value will only be visible on the port pin if the data direc- tion for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc2a register at the compare match between ocr2a and tcnt2, and clearing (or setting) the oc2a register at the timer clock cycle the counter is cleared (changes from max to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc2a to toggle its logical level on each compare match (com2a1:0 = 1). the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. phase correct pwm mode the phase correct pwm mode (wgm21:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phas e correct pwm mode is based on a dual- slope operation. the counter counts repeatedly from bottom to max and then from max to bottom. in non-inverting compare output mode, the output compare (oc2a) is cleared on the compare match between tcnt2 and ocr2a while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode is fixed to eight bits. in phase correct pwm mode the counter is incremented until the counter value matches max. when the counter reaches max, it changes the count direction. the tcnt2 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 68. the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes repre- sent compare matches between ocr2a and tcnt2. f ocnxpwm f clk_i/o n 256 ? ------------------ = 149 at90can128 4250e?can?12/04 figure 68. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bot- tom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2a pin. setting the com2a1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com2a1:0 to three (see table 69 on page 153). the actual oc2a value will only be visible on the port pin if the data direc- tion for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc2a register at the compare match between ocr2a and tcnt2 when the counter increments, and setting (or clearing) the oc2a register at compare match between ocr2a and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr2a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 150 at90can128 4250e?can?12/04 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 69 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 69. timer/counter timing diagram, no prescaling figure 70 shows the same timing data, but with the prescaler enabled. figure 70. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 71 shows the setting of ocf2a in all modes except ctc mode. figure 71. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 151 at90can128 4250e?can?12/04 figure 72 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 72. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) 8-bit timer/counter register description timer/counter2 control register a? tccr2a bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2a is written when operating in pwm mode. when writing a logical one to the foc2a bit, an immediate compare match is forced on the waveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 tccr2a read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 152 at90can128 4250e?can?12/04 bit 6, 3 ? wgm21:0: waveform generation mode these bits control the counting sequence of the counter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of oper- ation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes. see table 66 and ?modes of operation? on page 145. note: 1. the ctc2 and pwm2 bit definition names are now obsolete. use the wgm21:0 def- initions. however, the functionality and location of these bits are compatible with previous versions of the timer. bit 5:4 ? com2a1:0: compare match output mode a these bits control the output compare pi n (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit cor- responding to oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm21:0 bit setting. table 67 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to a normal or ctc mode (non-pwm). table 68 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. table 66. waveform generation mode bit description (1) mode wgm21 (ctc2) wgm20 (pwm2) timer/counter mode of operation top update of ocr2a at tov2 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr2a immediate max 31 1fast pwm 0xfftopmax table 67. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 toggle oc2a on compare match. 1 0 clear oc2a on compare match. 1 1 set oc2a on compare match. table 68. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 1 0 clear oc2a on compare match. set oc2a at top. 1 1 set oc2a on compare match. clear oc2a at top. 153 at90can128 4250e?can?12/04 note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 147 for more details. table 69 shows the com21:0 bit functionality when the wgm21:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect pwm mode? on page 148 for more details. bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 70. timer/counter2 register ? tcnt2 the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2a register. table 69. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 1 0 clear oc2a on compare match when up-counting. set oc2a on compare match when downcounting. 1 1 set oc2a on compare match when up-counting. clear oc2a on compare match when downcounting. table 70. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 154 at90can128 4250e?can?12/04 output compare register a ? ocr2a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. asynchronous operation of the timer/counter2 asynchronous status register ? assr bit 7..5 ? reserved bits these bits are reserved for future use. bit 4 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the crystal oscillator will only run when this bit is zero. bit 3 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/counter2 is clocked from the i/o clock, clk i/o and the crystal oscillator connected to the timer/counter2 oscillator (tosc) does nor run. when as2 is written to one, timer/counter2 is clocked from a crystal oscillator con- nected to the timer/counter2 oscillator (t osc) or from external clock on tosc1 depending on exclk setting. when the value of as2 is changed, the contents of tcnt2, ocr2a, and tccr2a might be corrupted. bit 2 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. bit 1 ? ocr2ub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. bit 0 ? tcr2ub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. when tccr2a has been updated from the temporary storage register, bit 76543210 ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 2 1 0 ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub assr read/write r r r r/w r/w r r r initial value 0 0 0 0 0 0 0 0 155 at90can128 4250e?can?12/04 this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. if a write is performed to any of the three timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional inter- rupt to occur. the mechanisms for reading tcnt2, ocr2a, and tccr2a are different. when read- ing tcnt2, the actual timer value is read. when reading ocr2a or tccr2a, the value in the temporary storage register is read. asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. warning: when switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2a, and tccr2a might be corrupted. a safe procedure for switching clock source is: 1. disable the timer/counter2 interrupts by clearing ocie2a and toie2. 2. select clock source by setting as2 and exclk as appropriate. 3. write new values to tcnt2, ocr2a, and tccr2a. 4. to switch to asynchronous operation: wait for tcn2ub, ocr2ub, and tcr2ub. 5. clear the timer/counter2 interrupt flags. 6. enable interrupts, if needed. the oscillator is optimized for use with a 32.768 khz watch crystal. the cpu main clock frequency must be more than four times the oscillator or external clock frequency. when writing to one of the registers t cnt2, ocr2a, or tccr2a, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the three mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2a write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. when entering power-save or extended standby mode after having written to tcnt2, ocr2a, or tccr2a, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2a or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the ocr2ub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. if timer/counter2 is used to wake the device up from power-save or extended standby mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re-entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in doubt whether the time before re-entering power-save mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 1. write a value to tccr2a, tcnt2, or ocr2a. 2. wait until the corresponding update busy flag in assr returns to zero. 156 at90can128 4250e?can?12/04 3. enter power-save or adc noise reduction mode. when the asynchronous operation is selected, the 32.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. description of wake up from power-save mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: 1. write any value to either of the registers ocr2a or tccr2a. 2. wait for the corresponding update busy flag to be cleared. 3. read tcnt2. during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. timer/counter2 interrupt mask register ? timsk2 bit 7..2 ? reserved bits these bits are reserved for future use. bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter2 interrupt flag register ? tifr2. bit 76543210 ??????ocie2atoie2timsk2 read/write r r r r r r r/w r/w initial value00000000 157 at90can128 4250e?can?12/04 bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. timer/counter2 interrupt flag register ? tifr2 bit 7..2 ? reserved bits these bits are reserved for future use. bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2 (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in timer/counter2. tov2 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. bit 76543210 ??????ocf2atov2tifr2 read/write r r r r r r r/w r/w initial value00000000 158 at90can128 4250e?can?12/04 timer/counter2 prescaler figure 73. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk io . by setting the as2 bit in assr, timer/counter2 is asyn- chronously clocked from the tosc oscillator or tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2. the oscillator is optimized for use with a 32.768 khz crystal. setting as2 and resetting exclk enables the tosc oscillator. figure 74. timer/counter2 crystal oscillator connections a external clock can also be used using tosc1 as input. setting as2 and exclk enables this configuration. figure 75. timer/counter2 external clock connections 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psr2 clear clk t2 0 1 t osc2 exclk 0 1 as2 exclk 32 khz oscillator enable t osc1 tosc 2 tosc 1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz tosc 2 tosc 1 nc e xternal clock signal 159 at90can128 4250e?can?12/04 for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psr2 bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. general timer/counter control register ? gtccr bit 1 ? psr2: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mode? on page 92 for a description of the timer/counter synchronization mode. bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psr2 psr310 gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 160 at90can128 4250e?can?12/04 output compare modulator - ocm overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0 and 1. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. a lower case ?x? replaces the output compare unit channel, in this case a or c. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a value and so on. the output compare modulator (ocm) allows generation of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8-bit timer/counter0. for more details about these timer/counters see ?16-bit timer/counter (timer/counter1 and timer/counter3)? on page 108 and ?8-bit timer/counter0 with pwm? on page 94. figure 76. output compare modulator, block diagram when the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram (figure 76). description the output compare unit 1c and output compare unit 0a shares the pb7 port pin for output. the outputs of the output compare units (oc1c and oc0a) overrides the nor- mal portb7 register when one of them is enabled (i.e., when comnx1:0 is not equal to zero). when both oc1c and oc0a are enabled at the same time, the modulator is automatically enabled. when the modulator is enabled the type of modulation (logical and or or) can be selected by the portb7 register. note that the ddrb7 controls the direction of the port independent of the comnx1:0 bit setting. the functional equivalent schematic of the modulator is shown on figure 77. the sche- matic includes part of the timer/counter units and the port b pin 7 output driver circuit. oc1c pin oc0a / oc1c / pb7 timer/counter 1 timer/counter 0 oc0a 161 at90can128 4250e?can?12/04 figure 77. output compare modulator, schematic timing example figure 78 illustrates the modulator in action. in this example the timer/counter1 is set to operate in fast pwm mode (non-inverted) and timer/counter0 uses ctc waveform mode with toggle compare output mode (comnx1:0 = 1). figure 78. output compare modulator, timing diagram in this example, timer/counter0 provides the carrier, while the modulating signal is gen- erated by the output compare unit c of the timer/counter1. resolution of the pwm signal the resolution of the pwm signal (oc1c) is reduced by the modulation. the reduction factor is equal to the number of system clock cycles of one period of the carrier (oc0a). in this example the resolution is reduced by a factor of two. the reason for the reduction is illustrated in figure 78 at the second and third period of the pb7 output when portb7 equals zero. the period 2 high time is one cycle longer than the period 3 high time, but the result on the pb7 output is equal in both periods. portb7 ddrb7 dq dq pin databus com0a1 com0a0 oc0a / oc1c / pb7 com1c1 com1c0 modulator 1 0 oc1c dq oc0a dq (from t/c1 waveform generator) (from t/c0 waveform generator) 0 1 vcc 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o 162 at90can128 4250e?can?12/04 serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90can128 and peripheral devices or between several avr devices. the at90can128 spi includes the following features: features full-duplex, three-wire synchronous data transfer master or slave operation lsb first or msb first data transfer seven programmable bit rates end of transmission interrupt flag write collision flag protection wake-up from idle mode double speed (ck/2) master spi mode figure 79. spi block diagram (1) note: 1. refer to figure 2 on page 4, and table 32 on page 71 for spi pin placement. the interconnection between master and slave cpus with spi is shown in figure 80. the system consists of two shift registers, and a master clock generator. the spi mas- ter initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to inter- spi2x spi2x divider /2/4/8/16/32/64/128 clk io 163 at90can128 4250e?can?12/04 change data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock gener- ator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 80. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. shift enable 164 at90can128 4250e?can?12/04 when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 71. for more details on automatic port overrides, refer to ?alternate port functions? on page 67. note: 1. see ?alternate functions of port b? on page 71 for a detailed description of how to define the direction of the user defined spi pins. table 71. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 165 at90can128 4250e?can?12/04 the following code examples show how to initialize the spi as a master and how to per- form a simple transmission. ddr_spi in the examples must be replaced by the actual data direction register con- trolling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. note: 1. the example code assumes that the part specific header file is included. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 168 at90can128 4250e?can?12/04 bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 81 and figure 82 for an example. the cpol func- tionality is summarized below: bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 81 and figure 82 for an example. the cpol functionality is summarized below: bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io fre- quency f clkio is shown in the following table: spi status register ? spsr table 72. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 73. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 74. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f clkio / 4 001 f clkio / 16 010 f clkio / 64 011 f clkio / 128 100 f clkio / 2 101 f clkio / 8 110 f clkio / 32 111 f clkio / 64 bit 76543210 spif wcol ? ? ? ? ? spi2x spsr read/write rrrrrrrr/w initial value00000000 169 at90can128 4250e?can?12/04 bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. bit 5..1 ? res: reserved bits these bits are reserved bits in the at90can128 and will always read as zero. bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 74). this means that the minimum sck period will be two cpu clock periods. when the spi is configured as slave, the spi is only guaran- teed to work at f clkio /4 or lower. the spi interface on the at90can128 is also used for program memory and eeprom downloading or uploading. see page 337 for serial programming and verification. spi data register ? spdr bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the regis- ter file and the spi shift register. writing to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 170 at90can128 4250e?can?12/04 data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 81 and figure 82. data bits are shifted out and latched in on oppo- site edges of the sck signal, ensuring sufficient time for data signals to stabilize. this is clearly seen by summarizing table 72 and table 73, as done below: figure 81. spi transfer format with cpha = 0 figure 82. spi transfer format with cpha = 1 table 75. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 171 at90can128 4250e?can?12/04 usart (usart0 and usart1) the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. the main features are: features full duplex operation (independent serial receive and transmit registers) asynchronous or synchronous operation master or slave clocked synchronous operation high resolution baud rate generator supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits odd or even parity generation an d parity check supported by hardware data overrun detection framing error detection noise filtering includes false start bit detection and digital low pass filter three separate interrupts on tx complete, tx data register empty and rx complete multi-processor communication mode double speed asynchronous communication mode dual usart the at90can128 has two usart?s, usart0 and usart1. the functionality for both usart?s is described below. usart0 and usart1 have different i/o registers as shown in ?register summary? on page 394. 172 at90can128 4250e?can?12/04 overview many register and bit references in this section are written in general form. a lower case ?n? replaces the usart number, in this case 0 and 1. however, when using the register or bit defines in a program, the precise form must be used, i.e., udr0 for accessing usart0 i/o data value and so on. a simplified block diagram of the usartn transmitter is shown in figure 83. cpu accessible i/o registers and i/o pins are shown in bold. figure 83. usartn block diagram (1) note: 1. refer to figure 2 on page 4, table 41 on page 78, and table 36 on page 74 for usartn pin placement. the dashed boxes in the block diagram separate the three main parts of the usartn (listed from the top): clock generator, trans mitter and receiver. control registers are shared by all units. the cloc k generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the trans- mitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a contin- uous transfer of data without any delay between frames. the receiver is the most complex part of the usartn module due to its clock and data recovery units. the parity generator ubrrn[h:l] udr n (transmit) ucsran ucsrbn ucsrcn baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn (receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus clkio sync logic clock generator transmitter receiver 173 at90can128 4250e?can?12/04 recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usartn supports four modes of clock operation: normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the umseln bit in usartn control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) controls whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 84 shows a block diagram of the clock generation logic. figure 84. usartn clock generation logic, block diagram signal description: txn clk transmitter clock (internal signal). rxn clk receiver base clock (internal signal). xn cki input from xck pin (internal signal). used for synchronous slave operation. xn cko clock output to xck pin (internal signal). used for synchronous master operation. f clk io system i/o clock frequency. internal clock generation ? baud rate generator internal clock generation is used for t he asynchronous and the synchronous master modes of operation. the description in this section refers to figure 84. the usartn baud rate register (ubrrn) and the down-counter connected to it func- tion as a programmable prescaler or baud rate generator. the down-counter, running at system clock ( f clk io ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a clock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f clk io /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state prescaling down-counter /2 ubrrn /4 /2 f clk ubrrn+1 sync register clk xckn pin txn clk u2xn umseln ddr_xckn 0 1 0 1 xn cki xn cko ddr_xckn rxn clk 0 1 1 0 edge detector ucpoln io io 174 at90can128 4250e?can?12/04 machine that uses 2, 8 or 16 states depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. table 76 contains equations for calculating the baud rate (in bits per second) and for calculating the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps). f clk io system i/o clock frequency. ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095). some examples of ubrrn values for some system clock frequencies are found in table 84 (see page 195). double speed operation (u2x) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchro- nous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. external clock external clocking is used by the synchronous slave modes of operation. the description in this section refers to figure 84 for details. external clock input from the xckn pin is sampled by a synchronization register to mini- mize the chance of meta-stability. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process introduces a two cpu clock period delay and therefore the max- imum external xckn clock frequency is limited by the following equation: note that f clk io depends on the stability of the system clock source. it is therefore recom- mended to add some margin to avoid possible loss of data due to frequency variations. table 76. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f clkio 16 ubrr n 1 + () ubrr n f clkio 16 baud ----------------------- - 1 ? = baud f clkio 8 ubrr n 1 + () ubrr n f clkio 8 baud -------------------- 1 ? = baud f clkio 2 ubrr n 1 + () ubrr n f clkio 2 baud -------------------- 1 ? = f xckn f clkio 4 --------------- - < 175 at90can128 4250e?can?12/04 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 85. synchronous mode xckn timing. the ucpoln bit ucrsnc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 85 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and sampled at rising xckn edge. serial frame a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. frame formats the usartn accepts all 30 combinations of the following as valid frame formats: 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. when a com- plete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (h igh) state. figure 86 illustrates the possible combinations of the frame formats. bits inside brackets are optional. figure 86. frame formats st start bit, always low. (n) data bits (0 to 8). rxdn / txdn xckn rxdn / txdn xckn ucpoln = 0 ucpoln = 1 sample sample 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame 176 at90can128 4250e?can?12/04 p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usartn is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiv er and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoing communica- tion for both the receiver and transmitter. the usartn character size (ucszn2:0) bits select the number of data bits in the frame. the usartn parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usartn stop bit select (usbsn) bit. the receiver ignores the second stop bit. an fen (frame error) will there- fore only be detected in the cases where the first stop bit is zero. parity bit calculation the parity bit is calculated by doing an excl usive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. usart initialization the usartn has to be initialized before any communication can take place. the initial- ization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usartn operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is writ- ten) if it is used for this purpose. p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 177 at90can128 4250e?can?12/04 the following simple usart0 initialization code examples show one assembly and one c function that are equal in functionality. the examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. the example code assumes that the part specific header file is included. more advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. however, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. assembly code example (1) usart0_init: ; set baud rate sts ubrr0h, r17 sts ubrr0l, r16 ; set frame format: 8data, no parity & 2 stop bits ldi r16, (0< 181 at90can128 4250e?can?12/04 the following code example shows a simple usart0 receive function based on polling of the receive complete (rxc0) flag. when using frames with less than eight bits the most significant bits of the data read from the udr0 will be masked to zero. the usart0 has to be initialized before the function can be used. note: 1. the example code assumes that the part specific header file is included. the function simply waits for data to be present in the receive buffer by checking the rxc0 flag, before reading the buffer and returning the value. receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn. this rule applies to the fen, dorn and upen status flags as well. read status from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fifo, will change. assembly code example (1) usart0_receive: ; wait for data to be received lds r18, ucsr0a sbrs r18, rxc0 rjmp usart0_receive ; get and return received data from buffer lds r16, udr0 ret c code example (1) unsigned char usart0_receive ( void ) { /* wait for data to be received */ while ( ! (ucsr0a & (1< 183 at90can128 4250e?can?12/04 receive complete flag and interrupt the usartn receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and consequently the rxcn bit will become zero. when the receive complete interrupt enable (rxcien) in ucsrnb is set, the usartn receive complete interrupt will be executed as long as the rxcn flag is set (provided that global interrupts are enabled). when interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new interrupt will occur once the interrupt routine terminates. receiver error flags the usartn receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart implementa- tions. none of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucs- rnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condi- tion. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility with future devices, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity chec k is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 176 and ?parity checker? on page 183. parity checker the parity checker is active when the high usartn parity mode (upmn1) bit is set. type of parity check to be performed (odd or even) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 184 at90can128 4250e?can?12/04 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i.e., the rxenn is set to zero) the receiver will no longer override the norm al function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost flushing the receive buffer the receiver buffer fifo will be flushed when t he receiver is disabled, i.e., the buffer will be emptied of its contents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udrn i/o loca- tion until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. the example code assumes that the part specific header file is included. asynchronous data reception the usartn includes a clock recovery and a data recovery unit for handling asynchro- nous data reception. the clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic samples and low pass filters each incoming bit, thereby improv- ing the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. asynchronous clock recovery the clock recovery logic synchronizes internal clock to the incoming serial frames. fig- ure 87 illustrates the sampling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horizontal arrows illustrate the synchronization variation due to the sampling process. note the larger time variation when using the double speed mode (u2xn = 1) of operation. samples denoted zero are samples done when the rxdn line is idle (i.e., no communication activity). assembly code example (1) usart0_flush: lds r16, ucsr0a sbrs r16, rxc0 ret lds r16, udr0 rjmp usart0_flush c code example (1) void usart0_flush ( void ) { unsigned char dummy; while (ucsr0a & (1< 186 at90can128 4250e?can?12/04 figure 89 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. figure 89. stop bit sampling and next start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 89. for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detec- tion influences the operational range of the receiver. asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 77) base frequency, the receiver will not be able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fas t is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. table 77 and table 78 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxdn sample (u2xn = 0) sample (u2xn = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 187 at90can128 4250e?can?12/04 the recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver?s system clock (xtal) will always have some minor instability over the supply voltage range and the temperature range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. in this case an ubrrn value that gives an acceptable low error can be used if possible. multi-processor communication mode setting the multi-processor communication mode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usartn receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bus. the trans- mitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. mpcm protocol if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address table 77. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 78. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 188 at90can128 4250e?can?12/04 and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will receive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. using mpcm for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txbn = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communi- cation mode: 1. all slave mcus are in multi-processor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data frames until a new address frame is received. the other slave mcus, which still have the mpcmn bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmitter and receiver use the same character size setting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. 189 at90can128 4250e?can?12/04 usart register description usart0 i/o data register ? udr0 usart1 i/o data register ? udr1 bit 7:0 ? rxbn7:0: receive data buffer (read access) bit 7:0 ? txbn7:0: transmit data buffer (write access) the usartn transmit data buffer register and usartn receive data buffer regis- ters share the same i/o address referred to as usartn data register or udrn. the transmit data buffer register (txbn) will be the destination for data written to the udrn register location. reading the udrn register location will return the contents of the receive data buffer register (rxbn). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrna register is set. data written to udrn when the udren flag is not set, will be ignored by the usartn transmitter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data in to the transmit shift register when the shift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo. the fifo will change its state whenever the receive buffer is accessed. usart0 control and status register a ? ucsr0a usart1 control and status register a ? ucsr1a bit 7 ? rxcn: usartn receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is dis- abled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). bit 76543210 rxb0[7:0] udr0 (read) txb0[7:0] udr0 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxb1[7:0] udr1 (read) txb1[7:0] udr1 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 ucsr0a read/write r r/w r r r r r/w r/w initial value00100000 bit 76543210 rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 ucsr1a read/write r r/w r r r r r/w r/w initial value00100000 190 at90can128 4250e?can?12/04 bit 6 ? txcn: usartn transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a trans- mit complete interrupt (see description of the txcien bit). bit 5 ? udren: usartn data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to zero when writing to ucsrna. bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. bit 2 ? upen: usartn parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. bit 1 ? u2xn: double the usartn transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec- tively doubling the transfer rate for asynchronous communication. bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcmn bit is writ- ten to one, all the incoming frames received by the usarnt receiver that do not contain address information will be ignored. the transmitter is unaffected by the mpcmn setting. for more detailed inform ation see ?multi-processor communication mode? on page 187. usart0 control and status register b ? ucsr0b bit 76543210 rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 ucsr0b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 191 at90can128 4250e?can?12/04 usart1 control and status register b ? ucsr1b bit 7 ? rxcien: rx complete interrupt enable writing this bit to one enables interrupt on the rxcn flag. a usartn receive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. bit 6 ? txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a usartn transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. bit 5 ? udrien: usartn data register empty interrupt enable writing this bit to one enables interrupt on the udren flag. a data register empty inter- rupt will be generated only if the udrien bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. bit 4 ? rxenn: receiver enable writing this bit to one enables the usartn receiver. the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. bit 3 ? txenn: transmitter enable writing this bit to one enables the usartn transmitter. the transmitter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not beco me effective until ongoing and pending transmis- sions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. w hen disabled, the transmitter will no longer override the txdn port. bit 2 ? ucszn2: character size the ucszn2 bits combined with the ucszn1:0 bit in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. bit 1 ? rxb8n: receive data bit 8 rxb8n is the ninth data bit of the received character when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. bit 0 ? txb8n: transmit data bit 8 txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. usart0 control and status register c ? ucsr0c bit 76543210 rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 ucsr1b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 bit 76543210 ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 ucsr0c read/write r r/w r/w r/w r/w r/w r/w r/w 192 at90can128 4250e?can?12/04 usart1 control and status register c ? ucsr1c bit 7 ? reserved bit this bit is reserved for future use. for compatibility with future devices, these bit must be written to zero when ucsrnc is written. bit 6 ? umseln: usartn mode select this bit selects between asynchronous and synchronous mode of operation. bit 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabled, the transmit- ter will automatically generate and send the pa rity of the transmitted data bits within each frame. the receiver will generate a parity value for the incoming data and com- pare it to the upmn0 setting. if a mismatch is detected, the upen flag in ucsrna will be set. bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. initial value00000110 bit 76543210 ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpo1l ucsr1c read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000110 table 79. umseln bit settings umseln mode 0 asynchronous operation 1 synchronous operation table 80. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 81. usbsn bit settings usbsn stop bit(s) 01-bit 12-bit 193 at90can128 4250e?can?12/04 bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xckn). usart0 baud rate registers ? ubrr0l and ubrr0h usart1 baud rate registers ? ubrr1l and ubrr1h table 82. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 100reserved 101reserved 110reserved 1119-bit table 83. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge bit 151413121110 9 8 ? ? ? ? ubrr0[11:8] ubrr0h ubrr0[7:0] ubrr0l 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 bit 151413121110 9 8 ? ? ? ? ubrr1[11:8] ubrr1h ubrr1[7:0] ubrr1l 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 194 at90can128 4250e?can?12/04 bit 15:12 ? reserved bits these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrnh is written. bit 11:0 ? ubrrn11:0: usartn baud rate register this is a 12-bit register which contains the usartn baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usartn baud rate. ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. writing ubrrnl will trigger an immediate update of the baud rate prescaler. 195 at90can128 4250e?can?12/04 examples of baud rate setting for standard crystal, resonator and external oscillator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the ubrrn set- tings in table 84 up to table 87. ubrrn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 186). the error values are calculated using the following equation: error[%] 1 baudrate closest match baudrate -------------------------------------------------------- ? ?? ?? 100% ? = table 84. examples of ubrrn settings for commonly frequencies baud rate (bps) f clk io = 1.0000 mhz f clk io = 1.8432 mhz f clk io = 2.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6-7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 38.5%8-3.5% 70.0%150.0% 8 -3.5% 16 2.1% 19.2k 28.5%6-7.0% 50.0%110.0% 6-7.0% 12 0.2% 28.8k 18.5%38.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 08.5%18.5% 1 0.0% 3 0.0% 18.5%38.5% 76.8k ? ? 1 -18.6% 1 -25.0% 20.0% 1 -18.6% 2 8.5% 115.2k ? ? 08.5% 0 0.0% 1 0.0% 08.5%18.5% 230.4k??????00.0%???? 250k???????????? 500k???????????? 1m???????????? max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kpbs 250 kbps 1. ubrrn = 0, error = 0.0% 196 at90can128 4250e?can?12/04 table 85. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 3.6864 mhz f clk io = 4.0000 mhz f clk io = 7.3728 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6-7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 30.0%70.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 10.0%30.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1-7.8%3-7.8% 500k ? ? 0-7.8% ? ? 0 0.0% 0-7.8%1-7.8% 1m?????????? 0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kpbs 921.6 kbps 1. ubrrn = 0, error = 0.0% 197 at90can128 4250e?can?12/04 table 86. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 8.0000 mhz f clk io = 10.000 mhz f clk io = 11.0592 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.0% 143 0.0% 14.4k 34 -0.8% 68 0.6% 42 0.9% 86 0.2% 47 0.0% 95 0.0% 19.2k 25 0.2% 51 0.2% 32 -1.4% 64 0.2% 35 0.0% 71 0.0% 28.8k 16 2.1% 34 -0.8% 21 -1.4% 42 0.9% 23 0.0% 47 0.0% 38.4k 12 0.2% 25 0.2% 15 1.8% 32 -1.4% 17 0.0% 35 0.0% 57.6k 8 -3.5% 16 2.1% 10 -1.5% 21 -1.4% 11 0.0% 23 0.0% 76.8k 6-7.0% 12 0.2% 71.9%151.8% 8 0.0% 17 0.0% 115.2k 3 8.5% 8 -3.5% 4 9.6% 10 -1.5% 5 0.0% 11 0.0% 230.4k 1 8.5% 3 8.5% 2 -16.8% 4 9.6% 20.0%50.0% 250k 1 0.0% 3 0.0% 2 -33.3% 40.0% 2-7.8%5-7.8% 500k 0 0.0% 1 0.0% ? ? 2-33.3% ?? 2-7.8% 1m??00.0%???????? max. (1) 0.5 mbps 1 mbps 625 kbps 1.25 mbps 691.2 kbps 1.3824 mbps 1. ubrrn = 0, error = 0.0% 198 at90can128 4250e?can?12/04 table 87. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 12.0000 mhz f clk io = 14.7456 mhz f clk io = 16.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 28.8k 25 0.2% 51 0.2% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 38.4k 19 -2.5% 38 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 57.6k 12 0.2% 25 0.2% 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 76.8k 9 -2.7% 19 -2.5% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 115.2k 6-8.9% 12 0.2% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 230.4k 2 11.3% 6 -8.9% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 0.0% 5 0.0% 3-7.8%6 5.3% 30.0%70.0% 500k ? ? 2 0.0% 1 -7.8% 3 -7.8% 10.0%30.0% 1m???? 0 -7.8% 1 -7.8% 00.0%10.0% max. (1) 750 kbps 1.5 mbps 921.6 kbps 1.8432 mbps 1 mbps 2 mbps 1. ubrrn = 0, error = 0.0% 199 at90can128 4250e?can?12/04 two-wire serial interface features simple yet powerful and flexible communication interface, only two bus lines needed both master and slave operation supported device can operate as transmitter or receiver 7-bit address space allows up to 128 different slave addresses multi-master arbitration support up to 400 khz data transfer speed slew-rate limited output drivers noise suppression circuitry rejects spikes on bus lines fully programmable slave addres s with general call support address recognition causes wake-up when avr is in sleep mode two-wire serial interface bus definition the two-wire serial interface (twi) is idea lly suited for typical microcontroller applica- tions. the twi protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hardware needed to implement the bus is a single pull-up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 90. twi bus interconnection twi terminology the following definitions are frequently encountered in this section. electrical interconnection as depicted in figure 90, both bus lines are connected to the positive supply voltage through pull-up resistors. the bus drivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and function which is essential to the opera- tion of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 88. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock slave the device addressed by a master transmitter the device placing data on the bus receiver the device reading data from the bus 200 at90can128 4250e?can?12/04 allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical characteristics of the twi is given in ?two-wire serial interface character- istics? on page 359. two different sets of specifications are presented there, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. data transfer and frame format transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 91. data validity start and stop conditions the master initiates and terminates a data transmission. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should tr y to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop con- dition. this is referred to as a repeated start condition, and is used when the master wishes to initiate a new transfer without relinquishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behaviour, and therefore start is used to describe both start and repeated start for the remainder of th is datasheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. figure 92. start, repeated start and stop conditions s da s cl data stable data stable data change s da s cl start sto p repeated start stop start 201 at90can128 4250e?can?12/04 address packet format all address packets transmitted on the twi bus are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is to be performed, otherwise a write operation should be per- formed. when a slave recognizes that it is being addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the master?s request, the sda line should be left high in the ack clock cycle. the master c an then transmit a st op condition, or a repeated start condition to initiate a new transmission. an address packet consist- ing of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allo- cated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same mes- sage to several slaves in the system. when the general call address followed by a write bit is transmitted on t he bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowledged the general call. note that transmitting the general call address followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 93. address packet format data packet format all data packets transmitted on the twi bus are 9 bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiv er is responsible for acknowledging the reception. an acknowledge (ack) is signa lled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. s da s cl start 12 789 addr msb addr lsb r/w ack 202 at90can128 4250e?can?12/04 figure 94. data packet format combining address and data packets into a transmission a transmission basically consists of a start condition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condition, is illegal. note that the wired-anding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the clock speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. the slave extending the scl low period will not affect the scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 95 shows a typical data transmission. note that several data bytes can be trans- mitted between the sla+r/w and the stop condition, depending on the software protocol implemented by the application software. figure 95. typical data transmission multi-master bus systems, arbitration and synchronization the twi protocol allows bus systems with several masters. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. two problems arise in multi-mas- ter systems: an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection process is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 12 789 data byte data msb data lsb ack s da s cl start 12 789 addr msb addr lsb r/w ack sla+r/w sto p 203 at90can128 4250e?can?12/04 same time should not be detectable to the slaves, i.e., the data being transferred on the bus must not be corrupted. different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will facilitate the arbitration process. the wired-anding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-anded, yielding a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 96. scl synchronization between multiple masters arbitration is carried out by all masters continuously monitoring the sda line after out- putting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checki ng if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will continue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will continue into the data packet. ta low ta high s cl from master a s cl from master b scl bus line tb low tb high masters start counting low period masters start counting high period 204 at90can128 4250e?can?12/04 figure 97. arbitration between two masters note that arbitration is not allowed between: a repeated start condition and a data bit a stop condition and a data bit a repeated start and a stop condition it is the user software?s responsibility to ens ure that these illegal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composition of sla+r/w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. sda from master a sda from master b sda line s ynchronized scl line start master a loses arbitration, sda a sda 205 at90can128 4250e?can?12/04 overview of the twi module the twi module is comprised of several submodules, as shown in figure 98. all regis- ters drawn in a thick line are accessible through the avr data bus. figure 98. overview of the twi module scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. note that the inter- nal pullups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is controlled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or pres- caler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: twbr = value of the twi bit rate register twps = value of the prescaler bits in the twi status register note: twbr should be 10 or higher if the twi operates in master mode. if twbr is lower than 10, the master may produce an incorrect output on sda and scl for the reminder of the byte. the problem occurs when operating the twi in master mode, sending start + sla + r/w to a slave (a slave does not need to be connected to the bus for the condition to happen). twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) scl frequency clkio 16 2(twbr) 4 twps ? + ----------------------------------------------------------- = 206 at90can128 4250e?can?12/04 bus interface unit this unit contains the data and address shift register (twdr), a start/stop con- troller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack register is not directly accessible by the applica- tion software. however, when receiving, it can be set or cleared by manipulating the twi control register (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for generation and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hardware continuously monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. address match unit the address match unit checks if received address bytes match the 7-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge its address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wakes up the cpu, the twi aborts operation and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down. control unit the control unit monitors the twi bus and generates responses corresponding to set- tings in the twi control register (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi status register (twsr) is updated with a status code identify- ing the event. the twsr only contains relevant status information when the twi interrupt flag is asserted. at all other times, the twsr contains a special status code indicating that no relevant status information is available. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: after the twi has transmitted a start/repeated start condition after the twi has transmitted sla+r/w after the twi has transmitted an address byte after the twi has lost arbitration after the twi has been addressed by own slave address or general call after the twi has received a data byte after a stop or repeated start has been received while still addressed as a slave when a bus error has occurred due to an illegal start or stop condition 207 at90can128 4250e?can?12/04 twi register description twi bit rate register ? twbr bits 7..0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 205 for calculating bit rates. twi control register ? twcr the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempted written to twdr while the register is inaccessible. bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects appli- cation software response. if the i-bit in sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cleared by hardware when executing the interrupt rou- tine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi status register (twsr), and twi data regis- ter (twdr) must be complete before clearing this flag. bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ack pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the two- wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the two-wire serial bus. the twi hardware checks if the bus is available, and generates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected, and then generates a new start condition to claim bit 76543210 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 208 at90can128 4250e?can?12/04 the bus master status. twsta must be cleared by software when the start condition has been transmitted. bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will generate a stop condition on the two-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared automatically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop condition, but the twi returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writing the twdr register when twint is high. bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates the twi interface. when twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. bit 1 ? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when twcr is written. bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in sreg is set, the twi interrupt request will be activated for as long as the twint flag is high. twi status register ? twsr bits 7..3 ? tws: twi status these 5 bits reflect the status of the twi logic and the two-wire serial bus. the differ- ent status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and t he 2-bit prescaler value. the application designer should mask the prescaler bits to zero when checking the status bits. this makes status checking independent of prescale r setting. this approach is used in this datasheet, unless otherwise noted. bit 2 ? res: reserved bit this bit is reserved and will always read as zero. bit 76543210 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value11111000 209 at90can128 4250e?can?12/04 bits 1..0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 205. the value of twps1..0 is used in the equation. twi data register ? twdr in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the first interrupt occurs. the data in twdr remains stable as long as twint is set. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. bits 7..0 ? twd: twi data register these eight bits constitute t he next data byte to be transmitted, or the latest data byte received on the twi serial bus. twi (slave) address register ? twar bits 7..1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. the twar should be loaded with the 7-bit slave address to which the twi will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. in multimaster sys- tems, twar must be set in masters which can be addressed as slaves by other masters. table 89. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 0 210 at90can128 4250e?can?12/04 bit 0 ? twgce: twi general call recognition enable bit twgce is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. if set, this bit enables the recogn ition of a general call given over the twi serial bus. 211 at90can128 4250e?can?12/04 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr together with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should generate an interrupt request. if the twie bit is cleared, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits applica- tion response. in this case, the twi status register (twsr) contains a value indicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 99 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this descrip- tion is quite abstract, a more detailed explanation follows later in this section. a simple code example implementing the desired behaviour is also presented. figure 99. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has successfully been sent. start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sendt, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicate s twint s et application action twi h ardware action 212 at90can128 4250e?can?12/04 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates other- wise, the application software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the address packet has successfully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any opera- tion as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has success- fully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must write a specific value to twcr, instructing the twi hardware to transmit a stop condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the appli- cation has cleared twint, the twi will initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows the principles involved in all twi transmis- sions. these can be summarized as follows: when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is cleared. when the twint flag is set, the user must update all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing twcr, the twint bit should be 213 at90can128 4250e?can?12/04 set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made for example by using include-files. assembly code example c example comments 1 ldi r16, (1< 215 at90can128 4250e?can?12/04 figure 100. data transfer in master transmitter mode a start condition is sent by writing the following value to twcr: twen must be set to enable the two-wire serial interface, twsta must be written to one to transmit a start condition and twint must be written to one to clear the twint flag. the twi will then test the two-wire serial bus and generate a start con- dition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 90). in order to enter mt mode, sla+w must be transmitted. this is done by writ- ing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an acknowledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible sta- tus codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 90. when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be written when twint is high. if not, the access will be discarded, and the write collision bit (twwc) will be set in the twcr register. after updating twdr, the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is gen- erated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver 216 at90can128 4250e?can?12/04 after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. table 90. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w x 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus be- comes free 217 at90can128 4250e?can?12/04 figure 101. formats and states in the master transmitter mode s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s 218 at90can128 4250e?can?12/04 master receiver mode in the master receiver mode, a number of data bytes are received from a slave trans- mitter (see figure 102). in order to enter a master mode, a start condition must be transmitted. the format of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 102. data transfer in master receiver mode a start condition is sent by writing the following value to twcr: twen must be written to one to enable the two-wire serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. the twi will then test the two-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the st atus code in twsr will be 0x08 (see table 90). in order to enter mr mode, sla+r must be transmitted. this is done by writing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+r have been transmitted and an acknowledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible sta- tus codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 101. received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 219 at90can128 4250e?can?12/04 after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. figure 103. formats and states in the master receiver mode s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a $58 a r s 220 at90can128 4250e?can?12/04 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master trans- mitter (see figure 104). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 104. data transfer in slave receiver mode to initiate the slave receiver mode, twar and twcr must be initialized as follows: table 91. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r x 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 221 at90can128 4250e?can?12/04 the upper seven bits are the address to which the two-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 92. the slave receiver mode may also be entered if arbi- tration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the two-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave address or the general call address by using the two-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be car- ried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the two-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 222 at90can128 4250e?can?12/04 table 92. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 223 at90can128 4250e?can?12/04 figure 105. formats and states in the slave receiver mode slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 106). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a 224 at90can128 4250e?can?12/04 figure 106. data transfer in slave transmitter mode to initiate the slave transmitter mode, twar and twcr must be initialized as follows: the upper seven bits are the address to which the two-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherwise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 93. the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transmit the last byte of the transfer. state 0xc0 or state 0xc8 will be entered, depending on whether the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has trans- mitted the last byte (twea zero and expecting nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the two-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave address or the general call address by using the two-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 225 at90can128 4250e?can?12/04 until the twint flag is cleared (by writing it to one). further data transmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the two-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. table 93. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 226 at90can128 4250e?can?12/04 figure 107. formats and states in the slave transmitter mode miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 94. status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a two-wire serial bus trans- fer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data fr om a serial eeprom. typically, such a transfer involves the following steps: s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a table 94. miscellaneous states status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. 227 at90can128 4250e?can?12/04 1. the transfer must be initiated 2. the eeprom must be instructed what location should be read 3. the reading must be performed 4. the transfer must be finished note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, requiring the use of the mt mode. sub- sequently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this prin- ciple is violated in a multimaster system, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data location. such a change in transfer direction is accomplished by transmitting a repeated start between the transmission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 108. combining several twi modes to access a serial eeprom multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simul- taneously by one or more of them. the twi standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the trans- fer, and that no data will be lost in the process. an example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. figure 109. an arbitration example several different scenarios may arise during arbitration, as described below: two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver slave receiver 228 at90can128 4250e?can?12/04 two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read/write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. two or more masters are accessing different slaves. in this case, arbitration will occur in the sla bits. masters trying to output a one on sda while another master outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 110. possible status values are given in circles. figure 110. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 229 at90can128 4250e?can?12/04 controller area network - can the controller area network (can) protocol is a real-time, serial, broadcast protocol with a very high level of security. the at90can128 can controller is fully compatible with the can specification 2.0 part a and part b. it delivers the features required to implement the kernel of the can bus protocol according to the iso/osi reference model: the data link layer - the logical link control (llc) sublayer - the medium access control (mac) sublayer the physical layer - the physical signalling (pls) sublayer - not supported - the physical medium attach (pma) - not supported - the medium dependent interface (mdi) the can controller is able to handle all types of frames (data, remote, error and over- load) and achieves a bitrate of 1 mbit/s. features full can controller fully compliant with can standard rev 2.0 a and rev 2.0 b 15 mob (message object) with their own: ? 11 bits of identifier tag (rev 2.0 a), 29 bits of identifier tag (rev 2.0 b) ? 11 bits of identifier mask (rev 2.0 a), 29 bits of identifier mask (rev 2.0 b) ? 8 bytes data buffer (static allocation) ? tx, rx, frame buffer or automatic reply configuration ? time stamping 1 mbit/s maximum transfer rate at 8 mhz ttc timer listening mode (for spying or autobaud) can protocol the can protocol is an international standard defined in the iso 11898 for high speed and iso 11519-2 for low speed. principles can is based on a broadcast communication mechanism. this broadcast communica- tion is achieved by usi ng a message oriented transmissi on protocol. these messages are identified by using a message identifier. such a message identifier has to be unique within the whole network and it defines not onl y the content but also the priority of the message. the priority at which a message is transmitted compared to another less urgent mes- sage is specified by the identifier of eac h message. the priorities are laid down during system design in the form of corre sponding binary values and cannot be changed dynamically. the identifier with the lowest binary number has the highest priority. bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. this happens in accordance with the "wired and" mechanism, by which the dominant state overwrites the recessive state. the com- petition for bus allocation is lost by all nodes with recessive transmission and dominant observation. all the "losers" automatically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. 230 at90can128 4250e?can?12/04 message formats the can protocol supports two message fram e formats, the only essential difference being in the length of the identifier. the can standard frame, also known as can 2.0 a, supports a length of 11 bits for the identifier, and the can extended frame, also known as can 2.0 b, supports a length of 29 bits for the identifier. can standard frame figure 111. can standard frames a message in the can standard frame format begins with the "start of frame (sof)", this is followed by the "arbitration field" wh ich consist of the identifier and the "remote transmission request (rtr)" bit used to distinguish between the data frame and the data request frame called remote frame. the following "control field" contains the "iden- tifier extension (ide)" bit and the "data length code (dlc)" used to indicate the number of following data bytes in the "data field". in a remote frame, the dlc contains the number of requested data bytes. the "data field" that follows can hold up to 8 data bytes. the frame integrity is guaranteed by the following "cyclic redundant check (crc)" sum. the "acknowledge (ack) field" compromises the ack slot and the ack delimiter. the bit in the ack slot is sent as a recessive bit and is overwritten as a domi- nant bit by the receivers which have at this time received the data correctly. correct messages are acknowledged by the receivers regardless of the result of the acceptance test. the end of the message is indicated by "end of frame (eof)". the "intermission frame space (ifs)" is the minimum number of bits separating consecutive messages. if there is no following bus access by any node, the bus remains idle. can extended frame figure 112. can extended frames 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc 0 - 8 bytes sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field data field data frame control field end of frame crc field ack field interframe space 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field remote frame control field end of frame crc field ack field interframe space 11-bit base identifier idt28..18 interframe space crc del. ack del. 15-bit crc 0 - 8 bytes sof sof srr ide ack 7 bits intermission 3 bits bus idle bus idle (indefinite ) arbitration field arbitration field data field data frame control field control field end of frame crc field ack field interframe space 11-bit base identifier idt28..18 18-bit identifier extension id17..0 18-bit identifier extension id17..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof srr ide r0 4-bit dlc dlc4..0 rtr rtr r0 r1 r1 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) remote frame end of frame crc field ack field interframe space 231 at90can128 4250e?can?12/04 a message in the can extended frame format is likely the same as a message in can standard frame format. the difference is the length of the identifier used. the identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identi- fier extension). the distinction between can standard frame format and can extended frame format is made by using the ide bit which is transmitted as dominant in case of a frame in can standard frame format, and transmitted as recessive in the other case. format co-existence as the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: the message in can standard frame format always has priority over the message in extended format. there are three different types of can modules available: ? 2.0a - considers 29 bit id as an error ? 2.0b passive - ignores 29 bit id messages ? 2.0b active - handles both 11 and 29 bit id messages can bit timing to ensure correct sampling up to the last bit, a can node needs to re-synchronize throughout the entire frame. this is done at the beginning of each message with the fall- ing edge sof and on each recessive to dominant edge. bit construction one can bit time is specified as four non-overlapping time segments. each segment is constructed from an integer multiple of the time quantum. the time quantum or tq is the smallest discrete timing resolution used by a can node. figure 113. can bit construction synchronization segment the first segment is used to synchronize the various bus nodes. on transmission, at the start of this segment, the current bit level is output. if there is a bit state change between the previous bit and the current bit, then the bus state change is expected to occur within this segment by the receiving nodes. propagation time segment this segment is used to compensate for signal delays across the network. this is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the bus nodes. time quantum (producer) nominal can bit time segments (producer) sync_seg prop_seg phase_seg_1 phase_seg_2 propagation delay segments (consumer) sync_seg prop_seg phase_seg_1 phase_seg_2 sample point transmission point (producer) can frame (producer) 232 at90can128 4250e?can?12/04 phase segment 1 phase segment 1 is used to compensate for edge phase errors. this segment may be lengthened during re-synchronization. sample point the sample point is the point of time at which the bus level is read and interpreted as the value of the respective bit. its location is at the end of phase segment 1 (between the two phase segments). phase segment 2 this segment is also used to compensate for edge phase errors. this segment may be shortened during re-synchronization, but the length has to be at least as long as the information processi ng time (ipt) and may not be more than the length of phase segment 1. information processing time it is the time required for the logic to determine the bit level of a sampled bit. the ipt begins at the sample point, is measured in tq and is fixed at 2tq for the atmel can. since phase segment 2 also begins at the sample point and is the last segment in the bit time, ps2 minimum shall not be less than the ipt. bit lengthening as a result of resynchronization, phase segment 1 may be lengthened or phase seg- ment 2 may be shortened to compensate for oscillator tolerances. if, for example, the transmitter oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. so phase segment 1 is lengthened in order to adjust the sample point and the end of the bit time. bit shortening if, on the other hand, the transmitter oscillator is fast er than the receiver one, the next falling edge used for resynchronization may be too early. so phase segment 2 in bit n is shortened in order to adjust the sample point for bit n+1 and the end of the bit time synchronization jump width the limit to the amount of lengthening or shortening of the phase segments is set by the resynchronization jump width. this segment may not be longer than phase segment 2. programming the sample point programming of the sample point allows "tuning" of the characteristics to suit the bus. early sampling allows more time quanta in the phase segment 2 so the synchroniza- tion jump width can be programmed to its maximum. this maximum capacity to shorten or lengthen the bit time decreases th e sensitivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used. late sampling allows more time quanta in the propagation time segment which allows a poorer bus topology and maximum bus length. synchronization hard synchronization occurs on the recessive-to-dominant transition of the start bit. the bit time is restarted from that edge. re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the synchronization segment in a message. arbitration the can protocol handles bus accesses according to the concept called ?carrier sense multiple access with arbitration on message priority?. during transmission, arbitration on the can bus can be lost to a competing device with a higher priority can identifier. this arbitr ation concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. 233 at90can128 4250e?can?12/04 the bus access conflict is resolved during the arbitration field mostly over the identifier value. if a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. rtr bit). figure 114. bus arbitration errors the can protocol signals any errors immediat ely as they occur. three error detection mechanisms are implemented at the message level and two at the bit level: error at message level cyclic redundancy check (crc) the crc safeguards the information in the frame by adding redundant check bits at the transmission end. at the receiver these bits are re-computed and tested against the received bits. if they do not agree there has been a crc error. frame check this mechanism verifies the structure of the transmitted frame by checking the bit fields against the fixed format and the frame size. errors detected by frame checks are designated "format errors". ack errors as already mentioned frames received are acknowledged by all receivers through positive acknowledgement. if no acknowledgement is received by the transmitter of the message an ack error is indicated. error at bit level monitoring the ability of the transmitter to detect errors is based on the monitoring of bus signals. each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. this permits reliable detection of global errors and errors local to the transmitter. bit stuffing the coding of the individual bits is tested at bit level. the bit representation used by can is "non return to zero (nrz)" coding, which guarantees maximum efficiency in bit coding. the synchronization edges are generated by means of bit stuffing. error signalling if one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". this prevents other nodes accepting the message and thus ensures the consistency of data throughout the net- work. after transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. node a txcan node b txcan id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 sof sof rtr ide can bus - - - - - - - - - arbitration lost node a loses the bus node b wins the bus 234 at90can128 4250e?can?12/04 can controller the can controller implemented into at90can128 offers v2.0b active. this full-can controller provides the whole hardware for convenient acceptance filtering and message management. for each message to be transmitted or received this mod- ule contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored. during the initialization of the peripheral, the application defines which messages are to be sent and which are to be received. only if the can controller receives a message whose identifier matches with one of the identifiers of the programmed (receive-) mes- sage objects the message is stored and the application is informed by interrupt. another advantage is that incoming remote frames can be answered automatically by the full- can controller with the corresponding data frame. in this way, the cpu load is strongly reduced compared to a basic-can solution. using full-can controller, high baudrates and high bus loads with many messages can be handled. figure 115. can controller structure can channel gen. control gen. status enable mob interrupt bit timing line error can timer lcc mac pls txd ca n rxd ca n mailbox message objets mob0 mob1 mob2 mob14 control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp buffer mob0 buffer mob1 buffer mob2 buffer mob14 can data buffers size=120 bytes low priority high priority mob scanning 235 at90can128 4250e?can?12/04 can channel configuration the can channel can be in: enabled mode in this mode: ? the can channel (internal txdcan & rxdcan) is enabled, ? the input clock is enabled. standby mode in standby mode: ? the transmitter constantly provides a recessive level (on internal txdcan) and the receiver is disabled, ? input clock is enabled, ? the registers and pages remain accessible. listening mode this mode is transparent for the can channel: ? enables a hardware loop back, internal txdcan on internal rxdcan ? provides a recessive level on txdcan pin ? does not disable rxdcan ? freezes tec and rec error counters figure 116. listening mode bit timing fsm?s (finite state machine) of the ca n channel need to be synchronous to the time quantum. so, the input clock for bit timing is the clock used into can channel fsm?s. field and segment abbreviations: brp: baud rate prescaler. tq: time quantum (output of baud rate prescaler). syns: synchronization segment is 1 tq long. prs: propagation time segment is programmable to be 1, 2, ..., 8 tq long. phs1: phase segment 1 is programmable to be 1, 2, ..., 8 tq long. phs2: phase segment 2 is programmable to be maximum of phs1 and information processing time. information processing time is 2 tq. sjw: (re) synchronization jump width is programmable to be minimum of phs1 and 4. the total number of tq in a bit time has to be programmed at least from 8 to 25. 1 0 pd5 txd ca n pd6 rxd ca n internal t xd can internal r xd can l isten 236 at90can128 4250e?can?12/04 figure 117. sample and transmission point figure 118. general structure of a bit period baud rate the baud rate selection is made by t bit calculation: tbit (1) = tsyns + tprs + tphs1 + tphs2 1. tsyns = 1 x tscl = (brp[5..0]+ 1)/clk io (= 1tq) 2.tprs = (1 to 8) x tscl = (prs[2..0]+ 1) x tscl 3.tphs1 = (1 to 8) x tscl = (phs1[2..0]+ 1) x tscl 4.tphs2 = (1 to 8) x tscl = (phs2[2..0] (2) + 1) x tscl 5.tsjw = (1 to 4) x tscl = (sjw[1..0]+ 1) x tscl notes: 1. the total number of tscl (time quanta) in a bit time must be between 8 to 25. 2. phs2[2..0] 2 is programmable to be maximum of phs1[2..0] and 1. fault confinement (c.f. section ?error management?). bit timing sample point transmission point prescaler brp prs (3-bit length) sjw (2-bit length) phs1 (3-bit length) phs2 (3-bit length) c lk io f can (tscl) time quantum bit rate prescaler clk io f can data tscl (tq) 1 / clk io one nominal bit tsyns(*) ( 1 ) phase error 0 ( 2 ) phase error 0 ( 3 ) phase error > 0 ( 4 ) phase error < 0 tphs2+tsjw ( 4 ) tphs1+tsjw ( 3 ) tbit tphs2 ( 2 ) tphs1 ( 1 ) tprs sample point transmission point ( * ) synchronization segment: syns tsyns=1 x tscl ( fixed ) 237 at90can128 4250e?can?12/04 overload frame an overload frame is sent by setting an overload request (ovrq). after the next recep- tion, the can channel sends an overl oad frame in accordance with the can specification. a status or flag is set (ovrf) as long as the overload frame is sent. figure 119. overload frame message objects the mob is a can frame descriptor. it contains all information to handle a can frame. this means that a mob has been outlined to allow to describe a can message like an object. the set of mobs is the front end part of the ?mailbox? where the messages to send and/or to receive are pre-defined as well as possible to decrease the work load of the software. the mobs are numbered from 0 up to 14 (no mob [15]). they are independent but pri- ority is given to the lower one in case of multi matching. the operating modes are: ? disabled mode ? transmit mode ? receive mode ? automatic reply ? frame buffer receive mode operating modes every mob has its own fields to control the operating mode. there is no default mode after reset. before enabling the can peripheral, each mob must be configured (ex: disabled mode - conmob=00). disabled in this mode, the mob is ?free?. tx data & remote frame 1. several fields must be initialized before sending: ? identifier tag (idt) ? identifier extension (ide) ident " a " cmd message data " a " crc interframe a ident " b " overload frame overload frame rxcan setting ovrq bit ovfg bit resetting ovrq bit txcan ovrq bit i nstructions table 95. mob configuration mob configuration reply valid rtr tag operating mode 00 x xdisabled 01 x 0 tx data frame x 1 tx remote frame 10 x 0 rx data frame 0 1 rx remote frame 1 rx remote frame then, tx data frame (reply) 1 1 x x frame buffer receive mode 238 at90can128 4250e?can?12/04 ? remote transmission request (rtrtag) ? data length code (dlc) ? reserved bit(s) tag (rbntag) ? data bytes of message (msg) 2. the mob is ready to send a data or a remote frame when the mob configuration is set (conmob). 3. then, the can channel scans all the mobs in tx configuration, finds the mob hav- ing the highest priority and tries to send it. 4. when the transmission is completed the txok flag is set (interrupt). 5. all the parameters and data are available in the mob until a new initialization. rx data & remote frame 1. several fields must be initialized before receiving: ? identifier tag (idt) ? identifier mask (idmsk) ? identifier extension (ide) ? identifier extension mask (idemsk) ? remote transmission request (rtrtag) ? remote transmission request mask (rtrmsk) ? data length code (dlc) ? reserved bit(s) tag (rbntag) 2. the mob is ready to receive a data or a remote frame when the mob configuration is set (conmob). 3. when a frame identifier is received on can network, the can channel scans all the mobs in receive mode, tries to find the mob having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the matched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched mob and the rxok flag is set (interrupt). 6. all the parameters and data are available in the mob until a new initialization. automatic reply a reply (data frame) to a remote frame can be automatically sent after reception of the expected remote frame. 1. several fields must be initialized before receiving the remote frame: ? (c.f. section ?rx data & remote frame?) 2. when a remote frame matches, automatically the rtrtag and the reply valid bit (rplv) are reset. no flag (or interrupt) is set at this time. since the can data buffer has not been used by the incoming remote frame, the mob is then ready to be in transmit mode without any more setting. the idt, the ide, the other tags and the dlc of the received remote frame are used for the reply. 3. when the transmission of the reply is completed the txok flag is set (interrupt). 4. all the parameters and data are available in the mob until a new initialization. frame buffer receive mode this mode is useful to receive multi frames. the priority between mobs offers a man- agement for these incoming frames. one set mobs (including non-consecutive mobs) is created when the mobs are set in this mode. due to the mode setting, only one set is possible. a frame buffer completed flag (or interrupt) - bxok - will rise only when all the mobs of the set will have received their dedicated can frame. 239 at90can128 4250e?can?12/04 1. mobs in frame buffer receive mode need to be initialized as mobs in standard receive mode. 2. the mobs are ready to receive data (or a remote) frames when their respective configurations are set (conmob). 3. when a frame identifier is received on can network, the can channel scans all the mobs in receive mode, tries to find the mob having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the matched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched mob and the rxok flag is set (interrupt). 6. when the reception in the last mob of the set is completed, the frame buffer com- pleted bxok flag is set (interrupt). bxok flag can be cleared only if all conmob fields of the set have been re-written before. 7. all the parameters and data are available in the mobs until a new initialization. acceptance filter upon a reception hit (i.e., a good comparison between the id + rtr + rbn + ide received and an idt+ rtrtag + rbntag + ide specified while taking the comparison mask into account) the idt + rtrtag + rbntag + ide received are updated in the mob (written over the registers). figure 120. acceptance filter block diagram note: examples: to accept only id = 0x317 in part a. to accept id from 0x310 up to 0x317 in part a. - id msk = 111 1111 1111 b - id msk = 111 1111 1000 b - id tag = 011 0001 0111 b - id tag = 011 0001 0xxx b mob page every mob is mapped into a page to save place. the page number is the mob number. this page number is set in canpage register. the number 15 is reserved for factory tests. canhpmob register gives the mob having the highest priority in cansit registers. it is formatted to provide a direct entry for canpage register. because canhpmob codes cansit registers, it will be only updated if the corresponding enable bits (enrx, entx, enerr) are enabled (c.f. figure 124). canidm registers ( mob[i] ) idmsk rtrmsk idemsk = canidt registers & cancdmob ( mob[i] ) id &rb rtrtag ide i nternal rxd can hit mob[ i] rx shift register (internal) id &rb rtr ide 13(32) 13(32) 13(32) 13(32) write enable 13(32) 1 240 at90can128 4250e?can?12/04 can data buffers to preserve register allocation, the can data buffer is seen such as a fifo (with address pointer accessible) into a mob selection.this also allows to reduce the risks of un-controlled accesses. there is one fifo per mob. this fifo is accessed into a mob page thanks to the can message register. the data index (indx) is the address pointer to the required data byte. the data byte can be read or write. the data index is automatically incremented after every access if the ainc* bit is reset. a roll-over is implemented, after data index=7 it is data index=0. the first byte of a can frame is stored at the data index=0, the second one at the data index=1, ... can timer a programmable 16-bit timer is used for message stamping and time trigger communi- cation (ttc). figure 121. can timer block diagram prescaler an 8-bit prescaler is initialized by cantcon register. it receives the clk io divided by 8. it provides clk cantim to the can timer if the can controller is enabled. clk cantim = clk io x 8 x (cantcon [7:0] + 1) 16-bit timer this timer starts counting from 0x0000 when the can controller is enabled (enfg bit). when the timer rolls over from 0xffff to 0x000 0, an interrupt is generated (ovrtim). time triggering two synchronization modes are implemented for ttc (ttc bit): ? synchronization on start of frame (syncttc=0), ? synchronization on end of frame (syncttc=1). in ttc mode, a frame is sent once, even if an error occurs. stamping message the capture of the timer value is done in the mob which receives or sends the frame. all managed mob are stamped, the stamping of a received (sent) frame occurs on rxok (txok). 8 c lk io clk cantim cantim canttc canstm[i] cantcon ttc syncttc " eof " " sof " ovrtim txok[i] r xok[i] overrun enfg 241 at90can128 4250e?can?12/04 error management fault confinement the can channel may be in one of the three following states: error active (default): the can channel takes part in bus communication and can send an active error frame when the can macro detects an error. error passive: the can channel cannot send an active error frame. it takes part in bus communication, but when an error is detected, a passive error frame is sent. also, after a transmission, an error passive unit will wait before initiating further transmission. bus off: the can channel is not allowed to have any influence on the bus. for fault confinement, a transmit error counter (tec) and a receive error counter (rec) are implemented. boff and errp bits give the information of the state of the can channel. setting boff to one may generate an interrupt. figure 122. line error mode note: more than one rec/tec change may apply during a given message transfer. error types berr : bit error. the bit value which is monitored is different from the bit value sent. note:exceptions: - recessive bit sent monitored as dominant bit during the arbitration field and the acknowledge slot. - detecting a dominant bit during the sending of an error frame. serr : stuff error. detection of more than five consecutive bit with the same polarity. cerr : crc error (rx only). the receiver performs a crc check on every destuffed received message from the start of frame up to the data field. if this checking does not match with the destuffed crc field, an crc error is set. ferr : form error. the form error results from one (or more) violations of the fixed form of the following bit fields: ? crc delimiter ? acknowledgement delimiter ? end-of-frame ? error delimiter erpp = 0 boff = 0 erpp = 0 boff = 1 erpp = 1 boff = 0 err or active err or p assive bus off tec > 127 or rec > 127 tec > 255 tec 127 and rec 127 128 occurrences of 11 consecutiv e recessiv e bit reset boffit interr upt 242 at90can128 4250e?can?12/04 ? overload delimiter aerr : acknowledgment error (tx only). no detection of the dominant bit in the acknowledge slot. figure 123. error detection procedures in a data frame error setting the can channel can detect some errors on the can network. in transmission: the error is set at mob level. in reception: - the identified has matched: the error is set at mob level. - the identified has not or not yet matched: the error is set at general level. after detecting an error, the can channel sends an error frame on network. if the can channel detects an error frame on network, it sends its own error frame. identifier message data rtr ack error form error stuff error bit error crc error form error stuff error bit error ack eof sof crc del. ack del. inter. command crc tx rx arbitration 243 at90can128 4250e?can?12/04 interrupts interrupt organization the different interrupts are: interrupt on receive completed ok, interrupt on transmit completed ok, interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), interrupt on frame buffer full, interrupt on ?bus off? setting, interrupt on overrun of can timer. the general interrupt enable is provided by enit bit and the specific interrupt enable for can timer overrun is provided by enorvt bit. figure 124. can controller interrupt structure txok[i] canstmob.6 rxok[i] canstmob.5 berr[i] canstmob.4 serr[i] canstmob.3 cerr[i] canstmob.2 ferr[i] canstmob.1 aerr[i] canstmob.0 bxok cangit.4 serg cangit.3 cerg cangit.2 ferg cangit.1 aerg cangit.0 boffi cangit.6 entx cangie.4 enrx cangie.5 enerr cangie.3 enbx cangie.2 energ cangie.1 enboff cangie.6 iemob[i] canie 1/2 enit cangie.7 enovrt cangie.0 sit[i] cansit 1/2 canit cangit.7 can it ovr it i=0 i=14 ovrtim cangit.5 244 at90can128 4250e?can?12/04 interrupt behavior when an interrupt occurs, the corresponding bit is set in the cansitn or cangit registers. to acknowledge a mob interrupt, the corresponding bits of canstmob register (rxok, txok,...) must be cleared by the software application. this operation needs a read-modify-write software routine. to acknowledge a general interrupt, the corresponding bits of cangit register (bxok, boffit,...) must be cleared by the software application. this operation is made writing a logical one in these interrupt flags (writing a logical zero doesn?t change the interrupt flag value). ovrtim interrupt flag is reset as the other interrupt sources of cangit register and is also reset entering in its dedicated interrupt handler. when the can node is in transmission and detects a form error in its frame, a bit error will also be raised. consequently, two consecutive interrupts can occur, both due to the same error. when a mob error occurs and is set in its own canstmob register, no general error is set in cangit register. 245 at90can128 4250e?can?12/04 can register description figure 125. registers organization general control general status general interrupt bit timing 1 bit timing 2 bit timing 3 enable mob 2 enable mob 1 enable interrupt status interrupt mob 2 status interrupt mob 1 enable interrupt mob 2 enable interrupt mob 1 can timer control can ttc low can ttc high can timer low can timer high tec counter rec counter hightest priority mob page mob mob number data index id tag 2 id tag 1 id tag 4 id tag 3 id mask 2 id mask 1 id mask 4 id mask 3 time stamp low time stamp high message data mob status mob control & dlc page mob mob0 - id tag 2 mob0 - id tag 1 mob0 - id tag 4 mob0 - id tag 3 mob0 - id mask 2 mob0 - id mask 1 mob0 - id mask 4 mob0 - id mask 3 mob0 - time stamp low mob0 - time stamp high mob0 - mob status mob0 - mob ctrl & dlc mob0 - mess. data - byte 0 mob14 - id tag 2 mob14 - id tag 1 mob14 - id tag 4 mob14 - id tag 3 mob14 - id mask 2 mob14 - id mask 1 mob14 - id mask 4 mob14 - id mask 3 mob14 - time stamp low mob14 - time stamp high mob14 - mob status mob14 - mob ctrl & dlc mob14 - mess. data - byte 0 15 message objects 8 b ytes a vr registers registers in p ages 246 at90can128 4250e?can?12/04 general can registers can general control register - cangcon bit 7 ? abrq: abort request this is not an auto resettable bit. ? 0 - no request. ? 1 - abort request: a reset of canen1 and canen2 registers is done. the pending communications are immediately disabled and the on-going one will be normally terminated, setting the appropriate status flags. note that concdmob register remain unchanged. bit 6 ? ovrq: overload frame request this is not an auto resettable bit. ? 0 - no request. ? 1 - overload frame request: send an overload frame after the next received frame. the overload frame can be traced observing ovfg in cangsta register (c.f. figure 119 on page 237). bit 5 ? ttc: time trigger communication ? 0 - no ttc. ?1- ttc mode. bit 4 ? synttc: synchronization of ttc this bit is only used in ttc mode. ? 0 - the ttc timer is caught on sof. ? 1 - the ttc timer is caught on the last bit of the eof. bit 3 ? listen: listening mode ? 0 - no listening mode. ? 1 - listening mode. bit 2 ? test: test mode ? 0 - no test mode ? 1 - test mode: intend for factory testing and not for customer use. note: can may malfunction if this bit is set. bit 1 ? ena/stb : enable / standby mode because this bit is a command and is not immediately effective, the enfg bit in cang- sta register gives the true state of the chosen mode. ? 0 - standby mode: the on-going communication is normally terminated and the can channel is frozen (the conmob bits of every mob do not change). the transmitter constantly provides a recessive level. in this mode, the receiver is not enabled but all the registers and mailbox remain accessible from cpu. ? 1 - enable mode: the can channel enters in enable mode once 11 recessive bits has been read. bit 76543210 abrq ovrq ttc synttc listen test ena/stb swres cangcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 247 at90can128 4250e?can?12/04 bit 0 ? swres: software reset request this auto resettable bit only resets the can controller. ? 0 - no reset ? 1 - reset: this reset is ?ored? with the hardware reset. can general status register - cangsta bit 7 ? reserved bit this bit is reserved for future use. bit 6 ? ovfg: overload frame flag this flag does not generate an interrupt. ? 0 - no overload frame. ? 1 - overload frame: set by hardware as long as the produced overload frame is sent. bit 5 ? reserved bit this bit is reserved for future use. bit 4 ? txbsy: transmitter busy this flag does not generate an interrupt. ? 0 - transmitter not busy. ? 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or error frame) or an ack field is sent. also set when an inter frame space is sent. bit 3 ? rxbsy: receiver busy this flag does not generate an interrupt. ? 0 - receiver not busy ? 1 - receiver busy: set by hardware as long as a frame is received or monitored. bit 2 ? enfg: enable flag this flag does not generate an interrupt. ? 0 - can controller disable: because an enable/disable command is not immediately effective, this status gives the true state of the chosen mode. ? 1 - can controller enable. bit 1 ? boff: bus off mode boff gives the information of the state of the can channel. only entering in bus off mode generates the boffit interrupt. ? 0 - no bus off mode. ? 1 - bus off mode. bit 76543210 - ovfg - txbsy rxbsy enfg boff errp cangsta read/write - r - r r r r r initial value - 0 - 0 0 0 0 0 248 at90can128 4250e?can?12/04 bit 0 ? errp: error passive mode errp gives the information of the state of the can channel. this flag does not generate an interrupt. ? 0 - no error passive mode. ? 1 - error passive mode. can general interrupt register - cangit bit 7 ? canit: general interrupt flag this is a read only bit. ? 0 - no interrupt. ? 1 - can interrupt: image of all the can controller interrupts except for ovrtim interrupt. this bit can be used for polling method. bit 6 ? boffit: bus off interrupt flag writing a logical one resets this interrupt flag. boffit flag is only set when the can enters in bus off mode coming from error passive mode. ? 0 - no interrupt. ? 1 - bus off interrupt when the can enters in bus off mode. bit 5 ? ovrtim: overrun can timer writing a logical one resets this interrupt flag. entering in can timer overrun interrupt handler also reset this interrupt flag ? 0 - no interrupt. ? 1 - can timer overrun interrupt: set when the can timer switches from 0xffff to 0x0000. bit 4 ? bxok: frame buffer receive interrupt writing a logical one resets this interrupt flag. bxok flag can be cleared only if all con- mob fields of the mob?s of the buffer have been re-written before. ? 0 - no interrupt. ? 1 - burst receive interrupt: set when the frame buffer receive is completed. bit 3 ? serg: stuff error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - stuff error interrupt: detection of more than five consecutive bits with the same polarity. bit 2 ? cerg: crc error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - crc error interrupt: the crc check on destuffed message does not fit with the crc field. bit 76543210 canit boffit ovrtim bxok serg cerg ferg aerg cangit read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 249 at90can128 4250e?can?12/04 bit 1 ? ferg: form error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - form error interrupt: one or more violations of the fixed form in the crc delimiter, acknowledgment delimiter or eof. bit 0 ? aerg: acknowledgment error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - acknowledgment error interrupt: no detection of the dominant bit in acknowledge slot. can general interrupt enable register - cangie bit 7 ? enit: enable all interrupts (except for can timer overrun interrupt) ? 0 - interrupt disabled. ? 1- canit interrupt enabled. bit 6 ? enboff: enable bus off interrupt ? 0 - interrupt disabled. ? 1- bus off interrupt enabled. bit 5 ? enrx: enable receive interrupt ? 0 - interrupt disabled. ? 1- receive interrupt enabled. bit 4 ? entx: enable transmit interrupt ? 0 - interrupt disabled. ? 1- transmit interrupt enabled. bit 3 ? enerr: enable mob errors interrupt ? 0 - interrupt disabled. ? 1- mob errors interrupt enabled. bit 2 ? enbx: enable frame buffer interrupt ? 0 - interrupt disabled. ? 1- frame buffer interrupt enabled. bit 1 ? energ: enable general errors interrupt ? 0 - interrupt disabled. ? 1- general errors interrupt enabled. bit 0 ? enovrt: enable can timer overrun interrupt ? 0 - interrupt disabled. ? 1- can timer interrupt overrun enabled. bit 76543210 enit enboff enrx entx enerr enbx energ enovrt cangie read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 250 at90can128 4250e?can?12/04 can enable mob registers - canen2 and canen1 bits 14:0 - enmob14:0: enable mob this bit provides the availability of the mob. it is set to one when the mob is enabled (i.e. conmob1:0 of cancdmob register). once txok or rxok is set to one (txok for automatic reply), the corresponding enmob is reset. enmob is also set to zero configuring the mob in disabled mode, applying abortion or standby mode. ? 0 - message object disabled: mob available for a new transmission or reception. ? 1 - message object enabled: mob in use. bit 15 ? reserved bit this bit is reserved for future use. can enable interrupt mob registers - canie2 and canie1 bits 14:0 - iemob14:0: interrupt enable by mob ? 0 - interrupt disabled. ? 1 - mob interrupt enabled note: example: canie2 = 0000 1100 b : enable of interrupts on mob 2 & 3. bit 15 ? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canie1 is written. can status interrupt mob registers - cansit2 and cansit1 bit 76543210 enmob7 enmob6 enmob5 enmob4 enmob3 enmob2 enmob1 enmob0 canen2 - enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 canen1 bit 151413121110 9 8 read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 read/write-rrrrrrr initial value - 0 0 0 0 0 0 0 bit 76543210 iemob7 iemob6 iemob5 iemob4 ie mob3 iemob2 iemob1 iemob0 canie2 - iemob14 iemob13 iemob12 iemob11 iemob10 iemob9 iemob8 canie1 bit 151413121110 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 read/write - r/w r/w r/w r/w r/w r/w r/w initial value- 0000000 bit 76543210 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 cansit2 - sit14 sit13 sit12 sit11 sit10 sit9 sit8 cansit1 bit 151413121110 9 8 read/writerrrrrrrr initial value00000000 read/write- rrrrrrr initial value- 0000000 251 at90can128 4250e?can?12/04 bits 14:0 - sit14:0: status of interrupt by mob ? 0 - no interrupt. ? 1- mob interrupt. note: example: cansit2 = 0010 0001 b : mob 0 & 5 interrupts. bit 15 ? reserved bit this bit is reserved for future use. can bit timing register 1 - canbt1 bit 7? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt1 is written. bit 6:1 ? brp5:0: baud rate prescaler the period of the can controller system clock tscl is programmable and determines the individual bit timing. bit 0 ? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt1 is written. can bit timing register 2 - canbt2 bit 7? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt2 is written. bit 6:5 ? sjw1:0: re-synchronization jump width to compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of clock cycles. a bit period may be shortened or lengthened by a re-synchronization. bit 4 ? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt2 is written. bit 76543210 - brp5 brp4 brp3 brp2 brp1 brp0 - canbt1 read/write - r/w r/w r/w r/w r/w r/w - initial value - 0 0 0 0 0 0 - tsc l = brp[5:0] + 1 clk io frequency bit 76543210 - sjw1 sjw0 - prs2 prs1 prs0 - canbt2 read/write - r/w r/w - r/w r/w r/w - initial value - 0 0 - 0 0 0 - tsjw = tscl x (sjw [1:0] +1) 252 at90can128 4250e?can?12/04 bit 3:1 ? prs2:0: propagation time segment this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal propagation time on the bus line, the input com- parator delay and the output driver delay. bit 0 ? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt2 is written. can bit timing register 3 - canbt3 bit 7? reserved bit this bit is reserved for future use. for compatibility with future devices, this must be writ- ten to zero when canbt3 is written. bit 6:4 ? phs22:0: phase segment 2 this phase is used to compensate for p hase edge errors. this segment may be short- ened by the re-synchronization jump width. phs2[2..0] shall be 1 and phs1[2..0] (c.f. section ?can bit timing? and section ?baud rate?). bit 3:1 ? phs12:0: phase segment 1 this phase is used to compensate for phase edge errors. this segment may be length- ened by the re-synchronization jump width. bit 0 ? smp: sample point(s) ? 0 - once, at the sample point. ? 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the tscl. the result corresponds to the majority decision of the three values. can timer control register - cantcon bit 7:0 ? tprsc7:0: can timer prescaler prescaler for the can timer upper counter r ange 0 to 255. it provides the clock to the can timer if the can controller is enabled. clk cantim = clk io x 8 x (cantcon [7:0] + 1) tprs = tscl x (prs [2:0] + 1) bit 76543210 - phs22 phs21 phs20 phs12 phs11 phs10 smp canbt3 read/write - r/w r/w r/w r/w r/w r/w r/w initial value- 0000000 tphs2 = tscl x (phs2 [2:0] + 1) tphs1 = tscl x (phs1 [2:0] + 1) bit 76543210 tprsc7 tprsc6 tprsc5 tprsc4 tprsc3 tprsc2 trpsc1 tprsc0 cantcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 253 at90can128 4250e?can?12/04 can timer registers - cantiml and cantimh bits 15:0 - cantim15:0: can timer count can timer counter range 0 to 65,535. can ttc timer registers - canttcl and canttch bits 15:0 - timttc15:0: ttc timer count can ttc timer counter range 0 to 65,535. can transmit error counter register - cantec bit 7:0 ? tec7:0: transmit error count can transmit error counter range 0 to 255. can receive error counter register - canrec bit 7:0 ? rec7:0: receive error count can receive error counter range 0 to 255. bit76543210 cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 cantim0 cantiml cantim15 cantim14 cantim13 cantim12 cantim11 cantim10 cantim9 cantim8 cantimh bit 1514131211109 8 read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 timttc0 canttcl timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 timttc9 timttc8 canttch bit 15141312111098 read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 cantec read/writerrrrrrrr initial value00000000 bit 76543210 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 canrec read/writerrrrrrrr initial value00000000 254 at90can128 4250e?can?12/04 can highest priority mob register - canhpmob bit 7:4 ? hpmob3:0: high est priority mob number mob having the highest priority in cansit registers. if cansit = 0 (no mob), the return value is 0xf. bit 3:0 ? cgp3:0: can general purpose bits these bits can be pre-programmed to matc h with the wanted configuration of the canpage register (i.e., ainc and indx2:0 setting). can page mob register - canpage bit 7:4 ? mobnb3:0: mob number selection of the mob number, the available numbers are from 0 to 14. bit 3 ? ainc : auto increment of the fifo can data buffer index (active low) ? 0 - auto increment of the index (default value). ? 1- no auto increment of the index. bit 2:0 ? indx2:0: fifo can data buffer index byte location of the can data byte into the fifo for the defined mob. mob registers the mob registers has no initial (default) value after reset. can mob status register - canstmob bit 7 ? dlcw: data length code warning the incoming message does not have the dlc expected. whatever the frame type, the dlc field of the cancdmob register is updated by the received dlc. bit 6 ? txok: transmit ok this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. the communication enabled by transmission is completed. when the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower mob index (0 to 14) is supplied first. bit 76543210 hpmob3 hpmob2 hpmob1 hpmob0 cgp3 cgp2 cgp1 cgp0 canhpmob read/write r r r r r/w r/w r/w r/w initial value 1 1 1 1 0 0 0 0 bit 76543210 mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 canpage read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 dlcw txok rxok berr serr cerr ferr aerr canstmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - 255 at90can128 4250e?can?12/04 bit 5 ? rxok: receive ok this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. the communication enabled by reception is completed. in the case of two or more mes- sage object reception hits, the lower mob index (0 to 14) is updated first. bit 4 ? berr: bit error (only in transmission) this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. the bit value monitored is different from the bit value sent. exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. bit 3 ? serr: stuff error this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. detection of more than five consecutive bits with the same polarity. this flag can gener- ate an interrupt. bit 2 ? cerr: crc error this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. the receiver performs a crc check on every de-stuffed received message from the start of frame up to the data field. if this checking does not match with the de-stuffed crc field, a crc error is set. bit 1 ? ferr: form error this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. the form error results from one or more violations of the fixed form in the following bit fields: crc delimiter. acknowledgment delimiter. eof bit 0 ? aerr: acknowledgment error this flag can generate an interrupt. it must be cleared using a read-modify-write soft- ware routine on the whole canstmob register. no detection of the dominant bit in the acknowledge slot. 256 at90can128 4250e?can?12/04 can mob control and dlc register - cancdmob bit 7:6 ? conmob1:0: configuration of message object these bits set the communication to be performed ( no initial value after reset). ? 00 - disable. ? 01 - enable transmission. ? 10 - enable reception. ? 11 - enable frame buffer reception these bits are not cleared once the communication is performed. the user must re- write the configuration to enable a new communication. this operation is necessary to be able to reset the bxok flag. this operation also set the corresponding bit in the canen registers. bit 5 ? rplv: reply valid used in the automatic reply mode after receiving a remote frame. ? 0 - reply not ready. ? 1 - reply ready and valid. bit 4 ? ide: identifier extension ide bit of the remote or data frame to send. this bit is updated with the corresponding value of the remote or data frame received. ? 0 - can standard rev 2.0 a (identifiers length = 11 bits). ? 1 - can standard rev 2.0 b (identifiers length = 29 bits). bit 3:0 ? dlc3:0: data length code number of bytes in the data field of the message. dlc field of the remote or data frame to send. the range of dlc is from 0 up to 8. if dlc field >8 then effective dlc=8. this field is updated with the corresponding value of the remote or data frame received. if the expected dlc differs from the incoming dlc, a dlc warning appears in the can- stmob register. bit 7 6 543210 conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 cancdmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - 257 at90can128 4250e?can?12/04 can identifier tag registers - canidt1, canidt2, canidt3, and canidt4 v2.0 part a v2.0 part b v2.0 part a bit 31:21 ? idt10:0: identifier tag identifier field of the remote or data frame to send. this field is updated with the corresponding value of the remote or data frame received. bit 20:3 ? reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when canidtn are written. when a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values. bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. bit 1 ? reserved bit this bit is reserved for future use. for compatibility with future devices, it must be written to zero when canidtn are written. when a remote or data frame is received, this bit does not operate in the comparison but it is updated with un-predicted values. bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. v2.0 part b bit 31:3 ? idt28:0: identifier tag identifier field of the remote or data frame to send. this field is updated with the corresponding value of the remote or data frame received. bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrtag - rb0tag canidt4 --------canidt3 idt 2 idt 1 idt 0-----canidt2 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 idt 4 idt 3canidt1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag canidt4 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5canidt3 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 canidt2 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 canidt1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - 258 at90can128 4250e?can?12/04 bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. bit 1 ? rb1tag: reserved bit 1 tag rb1 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. can identifier mask registers - canidm1, canidm2, canidm3, and canidm4 v2.0 part a v2.0 part b v2.0 part a bit 31:21 ? idmsk10:0: identifier mask ? 0 - comparison true forced ? 1 - bit comparison enabled. bit 20:3 ? reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when canidmn are written. bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced ? 1 - bit comparison enabled. bit 1 ? reserved bit this bit is reserved for future use. for compatibility with future devices, it must be written to zero when canidtn are written. bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrmsk - idemsk canidm4 - - - - - - - - canidm3 idmsk 2 idmsk 1 idmsk 0 - - - - - canidm2 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 idmsk 4 idmsk 3 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0 rtrmsk - idemsk canidm4 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 canidm3 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 canidm2 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - 259 at90can128 4250e?can?12/04 bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced ? 1 - bit comparison enabled. v2.0 part b bit 31:3 ? idmsk28:0: identifier mask ? 0 - comparison true forced ? 1 - bit comparison enabled. bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced ? 1 - bit comparison enabled. bit 1 ? reserved bit writing zero in this bit is recommended. bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced ? 1 - bit comparison enabled. can time stamp registers - canstml and canstmh bits 15:0 - timstm15:0: time stamp count can time stamp counter range 0 to 65,535. can data message register - canmsg bit 7:0 ? msg7:0: message data this register contains the can data byte pointed at the page mob register. after writing in the page mob register, this byte is equal to the specified message loca- tion of the pre-defined identifier + index. if auto-incrementation is used, at the end of the data register writing or reading cycle, the index is auto-incremented. the range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...). bit 76543210 timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 timstm0 canstml timstm15 timstm14 timstm13 timstm12 timstm11 timstm10 timstm9 timstm8 canstmh bit 151413121110 9 8 read/writerrrrrrrr initial value-------- bit 76543210 msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 canmsg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - 260 at90can128 4250e?can?12/04 examples of can baud rate setting the can bus requires very accurate timing especially for high baud rates. it is recom- mended to use only an external crystal for can operations. (refer to ?bit timing? on page 235 for timing description and page 251 to page 252 for ?can bit timing registers?). table 96. examples of can baud rate settings for commonly frequencies f clk io (mhz) can baud rate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3 16.000 1000 75 % 0.0625 16 7 4 4 1 0x00 0x0c 0x37 0.125832 21 0x02 0x04 0x13 500 75 % 0.125 16 7 4 4 1 0x02 0x0c 0x37 0.250832 21 0x06 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x06 0x0c 0x37 0.500832 21 0x0e 0x04 0x13 200 75 % 0.3125 16 7 4 4 1 0x08 0x0c 0x37 0.625832 21 0x12 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x0e 0x0c 0x37 1.000832 21 0x1e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x12 0x0c 0x37 1.350832 21 0x26 0x04 0x13 12.000 1000 75 % 0.083333 12 5 3 3 1 0x00 0x08 0x25 x - - - n o d a t a - - - 500 75 % 0.166666 12 5 3 3 1 0x02 0x08 0x25 0.250832 21 0x04 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x04 0x0c 0x37 0.500832 21 0x0a 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x04 0x0e 0x4b 0.416666 12 5 3 3 1 0x08 0x08 0x25 125 75 % 0.500 16 7 4 4 1 0x0a 0x0c 0x37 1.000832 21 0x16 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x0a 0x0e 0x4b 0.833333 12 5 3 3 1 0x12 0x08 0x25 261 at90can128 4250e?can?12/04 8.000 1000 75 % x - - - n o d a t a - - - 0.125832 21 0x00 0x04 0x13 500 75 % 0.125 16 7 4 4 1 0x00 0x0c 0x37 0.250832 21 0x02 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x02 0x0c 0x37 0.500832 21 0x06 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x02 0x0e 0x4b 0.625832 21 0x08 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x06 0x0c 0x37 1.000832 21 0x0e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x08 0x0c 0x37 1.350832 21 0x12 0x04 0x13 6.000 1000 - - - n o t a p p l i c a b l e - - - 500 75 % 0.166666 12 5 3 3 1 0x00 0x08 0x25 x - - - n o d a t a - - - 250 75 % 0.333333 12 5 3 3 1 0x02 0x08 0x25 0.500832 21 0x04 0x04 0x13 200 80 % 0.333333 15 7 4 3 1 0x02 0x0c 0x35 0.500 10 4 3 2 1 0x04 0x06 0x23 125 75 % 0.500 16 7 4 4 1 0x04 0x0c 0x37 1.000832 21 0x0a 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x04 0x0e 0x4b 0.833333 12 5 3 3 1 0x08 0x08 0x25 4.000 1000 - - - n o t a p p l i c a b l e - - - 500 75 % x - - - n o d a t a - - - 0.250832 21 0x00 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x00 0x0c 0x37 0.500832 21 0x02 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x00 0x0e 0x4b x - - - n o d a t a - - - 125 75 % 0.500 16 7 4 4 1 0x02 0x0c 0x37 1.000832 21 0x06 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x02 0x0e 0x4b 1.350 8 3 2 2 1 0x08 0x04 0x13 table 96. examples of can baud rate settings for commonly frequencies (continued) f clk io (mhz) can baud rate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3 262 at90can128 4250e?can?12/04 analog comparator the analog comparator compares the input values on the positive pin ain0 and nega- tive pin ain1. overview when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the com- parator and its surrounding logic is shown in figure 126 . figure 126. analog comparator block diagram (1)(2) notes: 1. adc multiplexer output: see table 98 on page 264. 2. refer to figure 2 on page 4 and table 41 on page 78 for analog comparator pin placement. analog comparator register description adc control and status register b ? adcsrb bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog compar- ator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 264. analog comparator control and status register ? acsr acbg bandgap reference adc multiplexer output acme aden t/c1 input captur e bit 7 6543210 adhsm acme ? ? ? adts2 adts1 adts0 adcsrb read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 263 at90can128 4250e?can?12/04 bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog compar- ator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference voltage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to the positive input of the analog comparator. see ?internal voltage reference? on page 52 bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the status register is set, the ana- log comparator interrupt is activated. when written logic zero, the interrupt is disabled. bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture inter- rupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator inter- rupt. the different settings are shown in table 97. table 97. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. 264 at90can128 4250e?can?12/04 when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the ana- log comparator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (aden in adcsra is zero), mux2..0 in admux select the input pin to replace the negative input to the ana- log comparator, as shown in table 98. if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. digital input disable register 1 ? didr1 bit 1, 0 ? ain1d, ain0d: ain1, ain0 digital input disable when this bit is written logi c one, the digital input buffer on the ain1/0 pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1/0 pi n and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 98. analog comparator multiplexed input acme aden mux2..0 analog comparator negative input 0x xxxain1 11 xxxain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 bit 76543210 ??????ain1dain0ddidr1 read/write r r r r r r r/w r/w initial value00000000 265 at90can128 4250e?can?12/04 analog to digital converter - adc features 10-bit resolution 0.5 lsb integral non-linearity 2 lsb absolute accuracy 65 - 260 s conversion time up to 15 ksps at maximum resolution eight multiplexed single ended input channels seven differential input channels optional left adjustment for adc result readout 0 - v cc adc input voltage range selectable 2.56 v adc reference voltage free running or single conversion mode adc start conversion by auto triggering on interrupt sources interrupt on adc conversion complete sleep mode noise canceler the at90can128 features a 10-bit successive approximation adc. the adc is con- nected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs constructed from the pins of port f. the single-ended voltage inputs refer to 0v (gnd). the device also supports 16 differential voltage input combinations. two of the differen- tial inputs (adc1, adc0 and adc3, adc2 ) are equipped with a programmable gain stage, providing amplification steps of 0 db (1x), 20 db (10x), or 46 db (200x) on the dif- ferential input voltage before the a/d conversion. seven differential analog input channels share a common negative terminal (adc1), while any other adc input can be selected as the positive input terminal. if 1x or 10x gain is used, 8-bit resolution can be expected. if 200x gain is used, 7-bit resolution can be expected. the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 127. the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 272 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the volt- age reference may be externally decoupled at the aref pin by a capacitor for better noise performance. 266 at90can128 4250e?can?12/04 figure 127. analog to digital converter block schematic adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags adhsm start 267 at90can128 4250e?can?12/04 operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v refer- ence voltage may be connected to the aref pi n by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage refer- ence, can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positive and negative inputs to the differential amplifier. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage refer- ence and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the con- version is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. starting a conversion a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto trig- gering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is started. this provides a method of starting conversions at fixed intervals. if the trigger signal is still set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger signal during conversion, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trig- ger a new conversion at the next interrupt event. 268 at90can128 4250e?can?12/04 figure 128. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has fini shed. the adc then operates in free run- ning mode, constantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive conversions independently of whether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conver- sion was started. prescaling and conversion timing figure 129. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. alternatively, setting the adhsm bit in adcsrb allows an increased adc clock frequency at the expense of higher power consumption. the adc module contains a prescaler, which generates an acceptable adc clock fre- quency from any cpu frequency above 100 khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset a den s tart 269 at90can128 4250e?can?12/04 when initiating a single ended conversion by setting the adsc bit in adcsra, the con- version starts at the following rising edge of the adc clock cycle. see ?differential channels? on page 270 for details on differential conversion timing. a normal conversion takes 13 adc clock cycl es. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of an first conversion. when a con- version is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediatel y after the conver- sion completes, while adsc remains high. for a summary of conversion times, see table 99. figure 130. adc timing diagram, first conversion (single conversion mode) figure 131. adc timing diagram, single conversion sign and msb of result lsb of result a dc clock a dsc sample & hold a dif a dch a dcl c ycle number a den 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and ref s update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result a dc clock a dsc a dif a dch a dcl c ycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and ref s update 270 at90can128 4250e?can?12/04 figure 132. adc timing diagram, auto triggered conversion figure 133. adc timing diagram, free running conversion differential channels when using differential channels, certain aspects of the conversion need to be taken into consideration. differential conversions are synchronized to the internal clock ck adc2 equal to half the adc clock frequency. this synchronization is done automatically by the adc interface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conver- sion initiated by the user (i.e., all single conversions, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (13 adc clock cycles from the next prescaled clock cycle). a conversion ini- tiated by the user when ck adc2 is high will take 14 adc clock cycles due to the synchronization mechanism. in free running mode, a new conversion is initiated imme- table 99. adc conversion time condition first conversion normal conversion, single ended auto triggered convertion sample & hold (cycles from start of convertion) 14.5 1.5 2 conversion time (cycles) 25 13 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of resul t lsb of result a dc clock t rigger s ource a dif a dch a dcl c ycle number 12 one conversion next conversio n conversion complete prescaler reset a date prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result a dc clock a dsc a dif a dch a dcl c ycle number 12 one conversion next conversion 34 conversion complete sample & ho ld mux and refs update 271 at90can128 4250e?can?12/04 diately after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the firs t) free running conversi ons will take 14 adc clock cycles. if differential channels are used and conversi ons are started by auto triggering, the adc must be switched off between conversion s. when auto triggering is used, the adc prescaler is reset before the conversion is started. since the stage is dependent of a stable adc clock prior to the conversion, this conversion will not be valid. by disabling and then re-enabling the adc between each conversion (writing aden in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see ?prescaling and conversion timing? on page 268 for tim- ing details. the gain stage is optimized for a bandwidth of 4 khz at all gain settings. higher frequen- cies may be subjected to non-linear amplification. an external low-pass filter should be used if the input signal contains higher frequency components than the gain stage band- width. note that the adc clock frequency is independent of the gain stage bandwidth limitation. e.g. the adc clock period may be 6 s, allowing a channel to be sampled at 12 ksps, regardless of the bandwidth of this channel. changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a tem- porary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and re ference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during conversion, minimum one adc clock cycle after the trigger event. 3. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differential channels. once a differential channel has been selected, the stage may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential channel. alternatively, conv ersion results obtained within this period should be discarded. the same settling time should be observed for the first differential conversion after changing adc reference (by changing the refs1:0 bits in admux). the settling time and gain stage bandwidth is independent of the adhsm bit setting. 272 at90can128 4250e?can?12/04 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. when switching to a differential gain chan nel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation cir- cuitry. the user should preferably disregard the first conversion result. adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is generated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be i naccurate, and the user is advised to dis- card this result. if differential channels are used, the selected reference should not be closer to av cc than indicated in table 140 on page 363. adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single con- version mode must be selected and the adc conversion complete interrupt must be enabled. 2. enter adc noise reduction mode (or idle mode). the adc will start a con- version once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc con- version is complete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion 273 at90can128 4250e?can?12/04 completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extended conversion to get a valid result. analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 134. an ana- log source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the adc. when the chan- nel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wi th an output impedance of approximately 10 k ? or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, wi th can vary widely. the user is recom- mended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the i nput circuitry looks somewhat different, although source impedances of a few hundred k ? or less is recommended. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 134. analog input circuitry analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 135. 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. a dcn i ih 1..100 k ? c s/h = 14 pf v cc /2 i il 274 at90can128 4250e?can?12/04 figure 135. adc power connections offset compensation schemes the gain stage has a built-in offset cancellation circuitry that nulls the offset of differen- tial measurements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. this offset residue can be then subtracted in software from the measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: vcc gnd 100nf analog ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 53 54 55 56 57 58 59 60 6161 6262 6363 6464 1 51 nc (ad0) pa0 10 h 275 at90can128 4250e?can?12/04 offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 136. offset error gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 137. gain error o utput code v ref input voltage ideal adc actual ad c offset error o utput code v ref input voltage ideal adc actual ad c gain error 276 at90can128 4250e?can?12/04 integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 138. integral non-linearity (inl) differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 139. differential non-linearity (dnl) quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. o utput code v ref input voltage ideal adc actual ad c inl o utput code 0x3ff 0x000 0 v ref input voltag e dnl 1 lsb 277 at90can128 4250e?can?12/04 adc conversion result after the conversion is complete (adif is high), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is: where v in is the voltage on the selected input pin and v ref the selected voltage refer- ence (see table 101 on page 279 and table 102 on page 280). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bit is zero, the result is positive. figure 140 shows the decoding of the differential input range. table 82 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a reference voltage of v ref . figure 140. differential measurement range adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? () gain 512 ?? v ref ------------------------------------------------------------------------ = 0 output code 0x1ff 0x000 v ref differential inp ut voltage (volts) 0x3ff 0x200 - v ref 278 at90can128 4250e?can?12/04 example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. table 100. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 279 at90can128 4250e?can?12/04 adc register description adc multiplexer selection register ? admux bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 101. if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see ?the adc data register ? adcl and adch? on page 282. bits 4:0 ? mux4:0: analog channel selection bits the value of these bits selects which combination of analog inputs are connected to the adc. these bits also select the gain for the differential channels. see table 102 for details. if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). bit 76543210 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 101. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal vref turned off 01av cc with external capacitor on aref pin 10reserved 1 1 internal 2.56v voltage reference with external capacitor on aref pin 280 at90can128 4250e?can?12/04 table 102. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 n/a (adc0 / adc0 / 10x) 01001 adc1 adc0 10x 01010 (adc0 / adc0 / 200x) 01011 adc1 adc0 200x 01100 (reserved - adc2 / adc2 / 10x) 01101 adc3 adc2 10x 01110 (adc2 / adc2 / 200x) 01111 adc3 adc2 200x 10000 adc0 adc1 1x 10001 (adc1 / adc1 / 1x) 10010 adc2 adc1 1x 10011 adc3 adc1 1x 10100 adc4 adc1 1x 10101 adc5 adc1 1x 10110 adc6 adc1 1x 10111 adc7 adc1 1x 11000 adc0 adc2 1x 11001 adc1 adc2 1x 11010 (adc2 / adc2 / 1x) 11011 adc3 adc2 1x 11100 adc4 adc2 1x 11101 adc5 adc2 1x 11110 1.1v (v band gap ) n/a 11111 0v (gnd) 281 at90can128 4250e?can?12/04 adc control and status register a ? adcsra bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, the adc is turned off. turn- ing the adc off while a conversion is in progress, will terminate this conversion. bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free run- ning mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. writing zero to this bit has no effect. bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto triggering of the adc is enabled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be dis- abled. this also applies if the sbi and cbi instructions are used. bit 3 ? adie: adc interrupt enable when this bit is written to one and the i- bit in sreg is set, the adc conversion com- plete interrupt is activated. bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 282 at90can128 4250e?can?12/04 bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. the adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the result is found in these two registers. if differ- ential channels are used, the result is presented in two?s complement form. when adcl is read, the adc data register is not updated until adch is read. conse- quently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. table 103. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 ?????? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ? ? ? ? ? adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 283 at90can128 4250e?can?12/04 adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 277. adc control and status register b ? adcsrb bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. this mode enables higher conversion rate at the expense of higher power consumption. bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selected interrupt flag. note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on t he trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trig- ger event, even if the adc interrupt flag is set . digital input disable register 0 ? didr0 bit 7:0 ? adc7d..adc0d: adc7:0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 adhsm acme ? ? ? adts2 adts1 adts0 adcsrb read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 104. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 284 at90can128 4250e?can?12/04 jtag interface and on-chip debug system features jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ? program counter ? eeprom and flash memories extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on single address or address range programming of flash, eeprom, fuses, and lock bits through the jtag interface on-chip debugging supported by avr studio ? overview the avr ieee std. 1149.1 compliant jtag interface can be used for: testing pcbs by using the jtag boundary-scan capability programming the non-volatile memories, fuses and lock bits on-chip debugging a brief description is given in the following sections. detailed descriptions for program- ming via the jtag interface, and using the boundary-scan chain can be found in the sections ?jtag programming overview? on page 342 and ?boundary-scan ieee 1149.1 (jtag)? on page 290 , respectively. the on-chip debug support is considered being pri- vate jtag instructions, and distributed within atmel and to selected third party vendors only. figure 141 shows a block diagram of the jtag interface and the on-chip debug sys- tem. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data reg- isters as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the behavior of a data register. the id-register (identifier register), bypass register, and the boundary-scan chain are the data registers used for board-level testing. the jtag programming interface (actually consisting of several physical and virtual data registers) is used for serial pro- gramming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. test access port ? tap the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: tms : test mode select. this pin is used for navigating through the tap-controller state machine. tck : test clock. jtag operation is synchronous to tck. tdi : test data in. serial input data to be shifted in to the instruction register or data register (scan chains). tdo : test data out. serial output data from instruction register or data register (scan chains). 285 at90can128 4250e?can?12/04 the ieee std. 1149.1 also specifies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is unprogrammed, these four tap pins are normal port pins and the tap controller is in reset. when programmed and the jtd bit in mcucr is cleared, the tap input signals are internally pulled high and the jtag is enabled for boundary-scan and programming. in this case, the tap output pin (tdo) is left floating in states where the jtag tap controller is not shifting data, and must therefore be con nected to a pull-up resistor or other hardware having pull-ups (for instance the tdi-input of the next device in the scan chain). the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is monitored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin low to reset the whole system, assuming only open collec- tors on the reset line are used in the application. figure 141. block diagram tap controller t di t do t ck t ms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pc instruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0 i/o port n boundary scan chain analog inputs control & clock lines device boundary 286 at90can128 4250e?can?12/04 figure 142. tap controller state diagram tap controller the tap controller is a 16-state finite state machine that controls the operation of the boundary-scan circuitry, jtag programming circuitry, or on-chip debug system. the state transitions depicted in figure 142 depend on the signal present on tms (shown adjacent to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test-logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a typical scenario for using the jtag inter- face is: at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. while in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in when this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 287 at90can128 4250e?can?12/04 apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update- dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data registers, and some jtag instructions may select certain functions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap controller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specification, refer to the literature listed in ?bibli- ography? on page 289. using the boundary- scan chain a complete description of the boundary-scan capabilities are given in the section ?boundary-scan ieee 1149.1 (jtag)? on page 290. using the on-chip debug system as shown in figure 141, the hardware support for on-chip debugging consists mainly of a scan chain on the interface between the internal avr cpu and the internal peripheral units. break point unit. communication interface between the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: 4 single program memory break points. 3 single program memory break points + 1 single data memory break point. 2 single program memory break points + 2 single data memory break points. 2 single program memory break points + 1 program memory break point with mask (?range break point?). 288 at90can128 4250e?can?12/04 2 single program memory break points + 1 data memory break point with mask (?range break point?). a debugger, like the avr studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. a list of the on-chip debug specific jtag instructions is given in ?on-chip debug spe- cific jtag instructions? on page 288. the jtagen fuse must be programmed to enable the jtag test access port. in addi- tion, the ocden fuse must be programmed and no lock bits must be set for the on- chip debug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chip debug system would have provided a back-door into a secured device. the avr studio enables the user to fully control execution of programs on an avr device with on-chip debug capability, avr in-circuit emulator, or the built-in avr instruction set simulator. avr studio ? supports source level execution of assembly programs assembled with atmel corporation?s avr assembler and c programs com- piled with third party vendors? compilers. avr studio runs under microsoft ? windows ? 95/98/2000/nt/xp. for a full description of the avr studio, please refer to the avr studio user guide. only highlights are presented in this document. all necessary execution commands are avail able in avr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instruction) and up to two data memory break points, alternatively combined as a mask (range) break point. on-chip debug specific jtag instructions the on-chip debug support is considered being private jtag instructions, and distrib- uted within atmel and to selected third party vendors only. instruction opcodes are listed for reference. private0 (0x8) private jtag instruction for accessing on-chip debug system. private1 (0x9) private jtag instruction for accessing on-chip debug system. private2 (0xa) private jtag instruction for accessing on-chip debug system. private3 (0xb) private jtag instruction for accessing on-chip debug system. on-chip debug related register in i/o memory on-chip debug register ? ocdr bit 7 6543210 idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 ocdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 289 at90can128 4250e?can?12/04 the ocdr register provides a communication channel from the running program in the microcontroller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an internal flag; i/o debug register dirty ? idrd ? is set to indicate to the debugger that the register has been written. when the cpu reads the ocdr register the 7 lsb will be from the ocdr register, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared with a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. refer to the debugger documentation for further information on how to use this register. using the jtag programming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag programming (in addition to power pins). it is not required to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mcucr register must be cleared to enable the jtag test access port. the jtag programming capability supports: flash programming and verifying. eeprom programming and verifying. fuse programming and verifying. lock bit programming and verifying. the lock bit security is exactly as in parallel programming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag instructions are given in the section ?jtag programming overview? on page 342. bibliography for more information about general boundary-scan, the following literature can be consulted: ieee: ieee std 1149.1-1990. ieee standard test access port and boundary-scan architecture, ieee, 1993. colin maunder: the board designers guide to testable logic circuits, addison- wesley, 1992. 290 at90can128 4250e?can?12/04 boundary-scan ieee 1149.1 (jtag) features jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities according to the jtag standard full scan of all port functions as well as analog circuitry having off-chip connections supports the optional idcode instruction additional public avr_reset instruction to reset the avr system overview the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-ch ip connections. at system level, all ics having jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan provides a mechanism for testing intercon- nections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag instructions idcode, bypass, sam- ple/preload, and extest, as well as the avr specific public jtag instruction avr_reset can be used for testing the printed circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. entering reset, the outputs of any port pin will inst antly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset instruction with appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/pre- load should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruct ion for the first time. sample/preload can also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be programmed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. data registers the data registers relevant for boundary-scan operations are: bypass register device identification register reset register boundary-scan chain bypass register the bypass register consists of a single shift register stage. when the bypass regis- ter is selected as path between tdi and tdo, the register is reset to 0 when leaving the 291 at90can128 4250e?can?12/04 capture-dr controller state. the bypass register may be used to shorten the scan chain on a system when the other devices are to be tested. device identification register figure 143 shows the structure of the device identification register. figure 143. the format of the device identification register version version is a 4-bit number identifying the revision of the component. the relevant version number is shown in table 105. part number the part number is a 16-bit code identifying the component. the jtag part number for at90can128 is listed in table 106. manufacturer id the manufacturer id is a 11-bit code identifying the manufacturer. the jtag manufac- turer id for atmel is listed in table 107. device id the full device id is listed in table 108 following the at90can128 version. reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also replace the function of the unimple- mented optional jtag instruction highz. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse settings for the clock options, the part will remain reset for a reset time-out period (refer to ?system clock? on page 34) after releasing the reset register. the out- msb lsb bit 31 2827 1211 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit table 105. jtag version numbers version jtag version number (hex) at90can128 revision a 0x0 table 106. avr jtag part number part number jtag part number (hex) at90can128 0x9781 table 107. manufacturer id manufacturer jtag manufactor id (hex) atmel 0x01f table 108. device id version jtag device id (hex) at90can128 revision a 0x0978103f 292 at90can128 4250e?can?12/04 put from this data register is not latched, so the reset will take place immediately, as shown in figure 144. figure 144. reset register boundary-scan chain the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 294 for a complete description. boundary-scan specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. listed below are the jtag instructions useful for boundary-scan operation. note that the optional highz instruction is not implemented, but all outputs with tri-state capability can be set in high- impedant state by using the avr_reset instru ction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. extest (0x0) mandatory jtag instruction for selecting the boundary-scan chain as data register for testing circuitry external to the avr pa ckage. for port-pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog cir- cuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. the contents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. the active states are: capture-dr : data on the external pins are sampled into the boundary-scan chain. shift-dr : the internal scan chain is shifted by the tck input. update-dr : data from the scan chain is applied to output pins. idcode (0x1) optional jtag instruction selecting the 32 bit id-register as data register. the id-reg- ister consists of a version number, a device number and the manufacturer code chosen by jedec. this is the default instruction after power-up. the active states are: capture-dr : data in the idcode register is sampled into the boundary-scan chain. shift-dr : the idcode scan chain is shifted by the tck input. dq from tdi clockdr avr_reset to tdo from other internal and external reset sources internal reset 293 at90can128 4250e?can?12/04 sample_preload (0x2) mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: capture-dr : data on the external pins are sampled into the boundary-scan chain. shift-dr : the boundary-scan chain is shifted by the tck input. update-dr : data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins. avr_reset (0xc) the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruc- tion. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: shift-dr : the reset register is shifted by the tck input. bypass (0xf) mandatory jtag instruction selecting the bypass register for data register. the active states are: capture-dr : loads a logic ?0? into the bypass register. shift-dr : the bypass register cell between tdi and tdo is shifted. boundary-scan related register in i/o memory mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is enabled if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in order to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to the desired value twice within four cycles to change its value. note that this bit must not be altered when using the on-chip debug system. if the jtag interface is left unconnected to other jtag circuitry, the jtd bit should be set to one. the reason for this is to avoid static current at the tdo pin in the jtag interface. bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 00000000 294 at90can128 4250e?can?12/04 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset by a power-on reset, or by writing a logic zero to the flag. boundary-scan chain the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection. scanning the digital port pins figure 145 shows the boundary-scan cell for a bi-directional port pin with pull-up func- tion. the cell consists of a standard boundary-scan cell for the pull-up enable ? puexn ? function, and a bi-directional pin cell that combines the three signals output control ? ocxn, output data ? odxn, and input data ? idxn, into only a two-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not included in the figures in the datasheet. figure 146 shows a simple digital port pin as described in the section ?i/o-ports? on page 61. the boundary-scan details from figure 145 replaces the dashed box in figure 146. when no alternate port function is present, the input data ? id ? corresponds to the pinxn register value (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the data direction ? dd register, and the pull-up enable ? puexn ? corresponds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 146 to make the scan chain read the actual pin value. for analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. bit 76543210 ? ? ?jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 295 at90can128 4250e?can?12/04 figure 145. boundary-scan cell for bi-directional port pin with pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 0 1 dq dq g 0 1 port pin (pxn) vcc extest to next cell shiftdr output control (oc) pullup enable (pue) output data (od) input data (id) from last cell updatedr clockdr ff2 ld2 ff1 ld1 ld0 ff0 296 at90can128 4250e?can?12/04 figure 146. general port pin schematic diagram boundary-scan and the two- wire interface the two two-wire interface pins scl and sda have one additional control signal in the scan-chain; two-wire interf ace enable ? twien. as shown in figure 147, the twien signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. a general scan cell as shown in figure 151 is attached to the twien signal. notes: 1. a separate scan chain for the 50 ns spike filter on the input is not provided. the ordi- nary scan support for digital port pins suffice for connectivity tests. the only reason for having twien in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-scan. 2. make sure the oc and twien signals are not asserted simultaneously, as this will lead to drive contention. clk rpx rrx wpx rdx wdx pud synchronizer wdx: write ddrx wpx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn 297 at90can128 4250e?can?12/04 figure 147. additional scan signal for the two-wire interface scanning the reset pin the reset pin accepts 3v or 5v active low logic for standard reset operation, and 12v active high logic for high voltage parallel programming. an observe-only cell as shown in figure 148 is inserted both for the 3v or 5v reset signal - rstt, and the 12v reset signal - rsthv. figure 148. observe-only cell for reset pin scanning the clock pins the avr devices have many clock options selectable by fuses. these are: internal rc oscillator, external clock, (high frequency) crystal oscillator, low-frequency crystal oscillator, and ceramic resonator. figure 149 shows how each oscillator with external connection is supported in the scan chain. the enable signal is supported with a general boundary-scan cell, while the oscillator/clock output is attached to an observe-only cell. in addition to the main clock, the timer2 oscillator is scanned in the same way. the output from the internal rc oscillator is not scanned, as this oscillator does not have external connections. pxn puexn odxn idxn twien ocxn slew-rate limited src 0 1 dq from previous cell clockdr shiftdr to next cell from system pin to system logic ff1 298 at90can128 4250e?can?12/04 figure 149. boundary-scan cells for oscillators and clock options table 109 summaries the scan registers for the external clock pin xtal1, oscillators with xtal1/xtal2 connections as well as external timer2 clock pin tosc1 and 32khz timer2 oscillator. notes: 1. do not enable more than one clock source as clock at a time. 2. scanning an oscillator output gives unpredictable results as there is a frequency drift between the internal oscillator and the jtag tck clock. if possible, scanning an external clock is preferred. 3. the main clock configuration is programmed by fuses. as a fuse is not changed run- time, the main clock configuration is considered fixed for a given application. the user is advised to scan the same clock option as to be used in the final system. the enable signals are supported in the scan chain because the system logic can disable clock options in sleep modes, thereby disconnecting the oscillator pins from the scan path if not provided. scanning the analog comparator the relevant comparator signals regarding boundary-scan are shown in figure 150. the boundary-scan cell from figure 151 is attached to each of these signals. the sig- nals are described in table 110. the comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. table 109. scan signals for the oscillators (1)(2)(3) enable signal scanned clock line clock option scanned clock line when not used extclken extclk (xtal1) external main clock 0 oscon oscck external crystal external ceramic resonator 1 osc32en osc32ck low freq. external crystal 1 toskon tosck 32 khz timer2 oscillator 1 0 1 dq from previous cell clockdr shiftdr to next cell to system logic ff1 0 1 dq dq g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest from digital logic xtal1 / tosc1 xtal2 / tosc2 oscillator enable output 299 at90can128 4250e?can?12/04 figure 150. analog comparator figure 151. general boundary-scan cell used for signals for comparator and adc table 110. boundary-scan signals for the analog comparator signal name direction as seen from the comparator description recommended input when not in use output values when recommended inputs are used ac_idle input turns off analog comparator when true 1 depends upon c code being executed aco output analog comparator output will become input to c code being executed 0 acme input uses output signal from adc mux when true 0 depends upon c code being executed acbg input bandgap reference enable 0 depends upon c code being executed acbg bandgap reference adc multiplexer output acme ac_idle aco adcen 0 1 dq dq g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest to analog circuitry / to digital logic from digital logic/ from analog ciruitry 300 at90can128 4250e?can?12/04 scanning the adc figure 152 shows a block diagram of the adc with all relevant control and observe sig- nals. the boundary-scan cell from figure 151 is attached to each of these signals. the adc need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. figure 152. analog to digital converter the signals are described briefly in table 111. + - aref prech dacout comp muxen_7 adc_7 muxen_6 adc_6 muxen_5 adc_5 muxen_4 adc_4 muxen_3 adc_3 muxen_2 adc_2 muxen_1 adc_1 muxen_0 adc_0 negsel_2 adc_2 negsel_1 adc_1 negsel_0 adc_0 extch + - + - 10x 20x 10-bit dac st aclk ampen 2.56v ref irefen aref vccren dac_9..0 adcen hold prech gnden passen acten comp sctest adcbgen to comparator g20 g10 1.22v ref adhsm adhsm table 111. boundary-scan signals for the adc (1) signal name direction as seen from the adc description recommen- ded input when not in use output values when recommended inputs are used, and cpu is not using the adc comp output comparator output 0 0 aclk input clock signal to gain stages implemented as switch-cap filters 00 acten input enable path from gain stages to the comparator 00 301 at90can128 4250e?can?12/04 adhsm input increases speed of comparator at the sacrifice of higher power consumption 00 adcbgen input enable band-gap reference as negative input to comparator 00 adcen input power-on signal to the adc 00 ampen input power-on signal to the gain stages 00 dac_9 input bit 9 of digital value to dac 11 dac_8 input bit 8 of digital value to dac 00 dac_7 input bit 7 of digital value to dac 00 dac_6 input bit 6 of digital value to dac 00 dac_5 input bit 5 of digital value to dac 00 dac_4 input bit 4 of digital value to dac 00 dac_3 input bit 3 of digital value to dac 00 dac_2 input bit 2 of digital value to dac 00 dac_1 input bit 1 of digital value to dac 00 dac_0 input bit 0 of digital value to dac 00 extch input connect adc channels 0 - 3 to by- pass path around gain stages 11 g10 input enable 10x gain 0 0 g20 input enable 20x gain 0 0 gnden input ground the negative input to comparator when true 00 table 111. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommen- ded input when not in use output values when recommended inputs are used, and cpu is not using the adc 302 at90can128 4250e?can?12/04 hold input sample & hold signal. sample analog signal when low. hold signal when high. if gain stages are used, this signal must go active when aclk is high. 11 irefen input enables band-gap reference as aref signal to dac 00 muxen_7 input input mux bit 7 0 0 muxen_6 input input mux bit 6 0 0 muxen_5 input input mux bit 5 0 0 muxen_4 input input mux bit 4 0 0 muxen_3 input input mux bit 3 0 0 muxen_2 input input mux bit 2 0 0 muxen_1 input input mux bit 1 0 0 muxen_0 input input mux bit 0 1 1 negsel_2 input input mux for negative input for differential signal, bit 2 00 negsel_1 input input mux for negative input for differential signal, bit 1 00 negsel_0 input input mux for negative input for differential signal, bit 0 00 passen input enable pass-gate of gain stages. 11 prech input precharge output latch of comparator. (active low) 11 table 111. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommen- ded input when not in use output values when recommended inputs are used, and cpu is not using the adc 303 at90can128 4250e?can?12/04 note: 1. incorrect setting of the switches in figure 152 will make signal contention and may damage the part. there are several input choices to the s&h circuitry on the negative input of the output comparator in figure 152. make sure only one path is selected from either one adc pin, bandgap reference source, or ground. if the adc is not to be used during scan, the recommended input values from table 111 should be used. the user is recommended not to use the differential gain stages dur- ing scan. switch-cap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. details concerning operations of the differential gain stage is therefore not provided. for the same reason, the adc high speed mode (adhsm) bit does not make any sense during boundary-scan operation. the avr adc is based on the analog circuitry shown in figure 152 with a successive approximation algorithm implemented in the digital logic. when used in boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. this can easily be done without running a successive approximation algorithm: apply the lower limit on the digital dac[9:0] lines, make sure the output from the com- parator is low, then apply the upper limit on the digital dac[9:0] lines, and verify the output from the comparator to be high. the adc need not be used for pure connectivi ty testing, since all analog inputs are shared with a digital port pin as well. when using the adc, remember the following the port pin for the adc channel in use must be configured to be an input with pull- up disabled to avoid signal contention. in normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the adc. the user is advised to wait at least 200ns after enabling the adc before controlling/observing any adc signal, or perform a dummy conversion before using the first result. the dac values must be stable at the midpoint value 0x200 when having the hold signal low (sample mode). sctest input switch-cap test enable. output from x10 gain stage send out to port pin having adc_4 00 st input output of gain stages will settle faster if this signal is high first two aclk periods after ampen goes high. 00 vccren input selects vcc as the acc reference voltage. 00 table 111. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommen- ded input when not in use output values when recommended inputs are used, and cpu is not using the adc 304 at90can128 4250e?can?12/04 as an example, consider the task of verifying a 1.5v 5% input signal at adc channel 3 when the power supply is 5.0v and aref is externally connected to v cc . the recommended values from table 111 are used unless other values are given in the algorithm in table 112. only the dac and port pin values of the scan chain are shown. the column ?actions? describes what jtag instruction to be used before filling the boundary-scan register with the succeeding columns. the verification should be done on the data scanned out when scanning in the data on the same row in the table. using this algorithm, the timing constraint on the hold signal constrains the tck clock frequency. as the algorithm keeps hold high for five steps, the tck clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, t hold,max table 112. algorithm for using the adc step actions adcen dac muxen hold prech pa3. data pa3. control pa3. pullup_ enable 1 sample_ preload 1 0x200 0x08 1 1 0 0 0 2 extest 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 6 verify the comp bit scanned out to be 0 1 0x200 0x08 1 1 0 0 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 11 verify the comp bit scanned out to be 1 1 0x200 0x08 1 1 0 0 0 the lower limit is: 1024 1,5 v 0,95 5 v ? ?? 291 0x123 == the upper limit is: 1024 1,5 v 1,05 5 v ? ?? 323 0x143 == 305 at90can128 4250e?can?12/04 at90can128 boundary- scan order table 113 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as possible. therefore, the bits of port a is scanned in the opposite bit order of the other ports. exceptions from the rules are the scan chains for the analog circ uits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. in figure 145, pxn. data corresponds to ff0, pxn. control corresponds to ff1, and pxn. pullup_enable corresponds to ff2. bit 2, 3, 4, and 5 of port c is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. table 113. at90can128 boundary-scan order bit number signal name comment module 200 ac_idle comparator 199 aco 198 acme 197 ainbg 196 comp adc 195 aclk 194 acten 193 adhsm 192 adcbgen 191 adcen 190 ampen 189 dac_9 188 dac_8 187 dac_7 186 dac_6 185 dac_5 184 dac_4 183 dac_3 182 dac_2 181 dac_1 180 dac_0 179 extch 178 g10 177 g20 176 gnden 175 hold 174 irefen 173 muxen_7 172 muxen_6 171 muxen_5 170 muxen_4 306 at90can128 4250e?can?12/04 169 muxen_3 adc 168 muxen_2 167 muxen_1 166 muxen_0 165 negsel_2 164 negsel_1 163 negsel_0 162 passen 161 prech 160 sctest 159 st 158 vccren 157 pe0.data port e 156 pe0.control 155 pe0.pullup_enable 154 pe1.data 153 pe1.control 152 pe1.pullup_enable 151 pe2.data 150 pe2.control 149 pe2.pullup_enable 148 pe3.data 147 pe3.control 146 pe3.pullup_enable 145 pe4.data 144 pe4.control 143 pe4.pullup_enable 142 pe5.data 141 pe5.control 140 pe5.pullup_enable 139 pe6.data 138 pe6.control 137 pe6.pullup_enable 136 pe7.data 135 pe7.control 134 pe7.pullup_enable 133 pb0.data port b 132 pb0.control table 113. at90can128 boundary-scan order (continued) bit number signal name comment module 307 at90can128 4250e?can?12/04 131 pb0.pullup_enable port b 130 pb1.data 129 pb1.control 128 pb1.pullup_enable 127 pb2.data 126 pb2.control 125 pb2.pullup_enable 124 pb3.data 123 pb3.control 122 pb3.pullup_enable 121 pb4.data 120 pb4.control 119 pb4.pullup_enable 118 pb5.data 117 pb5.control 116 pb5.pullup_enable 115 pb6.data 114 pb6.control 113 pb6.pullup_enable 112 pb7.data 111 pb7.control 110 pb7.pullup_enable 109 pg3.data port g 108 pg3.control 107 pg3.pullup_enable 106 pg4.data 105 pg4.control 104 pg4.pullup_enable 103 - (private signal) 102 rstt (observe only) reset logic 101 rsthv 100 extclken oscillators 99 oscon 98 osc32en 97 toskon 96 extclk (xtal1) 95 oscck 94 osc32ck table 113. at90can128 boundary-scan order (continued) bit number signal name comment module 308 at90can128 4250e?can?12/04 93 tosk oscillators 92 pd0.data port d 91 pd0.control 90 pd0.pullup_enable 89 pd1.data 88 pd1.control 87 pd1.pullup_enable 86 pd2.data 85 pd2.control 84 pd2.pullup_enable 83 pd3.data 82 pd3.control 81 pd3.pullup_enable 80 pd4.data 79 pd4.control 78 pd4.pullup_enable 77 pd5.data 76 pd5.control 75 pd5.pullup_enable 74 pd6.data 73 pd6.control 72 pd6.pullup_enable 71 pd7.data 70 pd7.control 69 pd7.pullup_enable 68 pg0.data port g 67 pg0.control 66 pg0.pullup_enable 65 pg1.data 64 pg1.control 63 pg1.pullup_enable 62 pc0.data port c 61 pc0.control 60 pc0.pullup_enable 59 pc1.data 58 pc1.control 57 pc1.pullup_enable 56 pc2.data table 113. at90can128 boundary-scan order (continued) bit number signal name comment module 309 at90can128 4250e?can?12/04 55 pc2.control port c 54 pc2.pullup_enable 53 pc3.data 52 pc3.control 51 pc3.pullup_enable 50 pc4.data 49 pc4.control 48 pc4.pullup_enable 47 pc5.data 46 pc5.control 45 pc5.pullup_enable 44 pc6.data 43 pc6.control 42 pc6.pullup_enable 41 pc7.data 40 pc7.control 39 pc7.pullup_enable 38 pg2.data port g 37 pg2.control 36 pg2.pullup_enable 35 pa7.data port a 34 pa7.control 33 pa7.pullup_enable 32 pa6.data 31 pa6.control 30 pa6.pullup_enable 29 pa5.data 28 pa5.control 27 pa5.pullup_enable 26 pa4.data 25 pa4.control 24 pa4.pullup_enable 23 pa3.data 22 pa3.control 21 pa3.pullup_enable 20 pa2.data 19 pa2.control 18 pa2.pullup_enable table 113. at90can128 boundary-scan order (continued) bit number signal name comment module 310 at90can128 4250e?can?12/04 boundary-scan description language files boundary-scan description language (bsdl) files describe boundary-scan capable devices in a standard format used by automated test-generation software. the order and function of bits in the boundary-scan data register are included in this description. a bsdl file for at90can128 is available. 17 pa1.data port a 16 pa1.control 15 pa1.pullup_enable 14 pa0.data 13 pa0.control 12 pa0.pullup_enable 11 pf3.data port f 10 pf3.control 9 pf3.pullup_enable 8pf2.data 7 pf2.control 6 pf2.pullup_enable 5pf1.data 4 pf1.control 3 pf1.pullup_enable 2pf0.data 1 pf0.control 0 pf0.pullup_enable table 113. at90can128 boundary-scan order (continued) bit number signal name comment module 311 at90can128 4250e?can?12/04 boot loader support ? read-w hile-write self-programming the boot loader support provides a real read-while-write self-programming mecha- nism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates controlled by the mcu using a flash-resi- dent boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different levels of protection. features read-while-write self-programming flexible boot memory size high security (separate boot lock bits for a flexible protection) separate fuse to select reset vector optimized page (1) size code efficient algorithm efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 131 on page 330) used during programming. the page organization does not affect normal operation. application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 154). the size of the different sections is configured by the bootsz fuses as shown in table 119 on page 323 and figure 154. these two sections can have different level of protection since they have different sets of lock bits. as - application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (blb02 and blb01 bits), see table 115 on page 315. the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. bls ? boot loader section while the application section is used for storing the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a pro- gramming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (blb12 and blb11 bits), see table 116 on page 315. read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader software update is dependent on which address that is being programmed. in addition to the two sections that are conf igurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write (rww) section and the no read-while-write (nrww) section. the limit between the rww- and nrww sections is given in table 120 on page 323 and figure 154 on page 314. the main difference between the two sections is: 312 at90can128 4250e?can?12/04 when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section during a boot loader software operation. the syntax ?read-while-write sec- tion? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww sec- tion. during an on-going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader section. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory control and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see ?store pro- gram memory control and status register ? spmcsr? on page 316 for details on how to clear rwwsb. nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 114. read-while-write features which section does the z- pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 313 at90can128 4250e?can?12/04 figure 153. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 314 at90can128 4250e?can?12/04 figure 154. memory sections note: 1. the parameters in the figure above are given in table 119 on page 323. boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set indepen- dently. this gives the user a unique flexibility to select different levels of protection. the user can select: to protect the entire flash from a software update by the mcu. to protect only the boot loader flash section from a software update by the mcu. to protect only the application flash section from a software update by the mcu. allow software update in the entire flash. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 315 at90can128 4250e?can?12/04 see table 115 and table 116 for further details. the boot lock bits can be set in soft- ware and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm (load program memory / store program memory) instructions, if it is attempted. note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi inter- face. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start execut- ing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always table 115. boot lock bit0 protection modes (application section) (1) lock bit mode blb02 blb01 protection 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 3 0 0 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 116. boot lock bit1 protection modes (boot loader section) (1) lock bit mode blb12 blb11 protection 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 316 at90can128 4250e?can?12/04 point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed store program memory control and status register ? spmcsr the store program memory control and status register contains the control bits needed to control the boot loader operations. bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alternatively the rwwsb bit will automatically be cleared if a page load operation is initiated. bit 5 ? res: reserved bit this bit is a reserved bit in the at90can128 and always read as zero. bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww section, the user software must wait until the programming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycl es re-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is written while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z-pointer/rampz are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles after blbset and spmen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in table 117. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 119 on page 323) bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 317 at90can128 4250e?can?12/04 the z-pointer) into the destination register . see ?reading the fuse and lock bits from software? on page 320 for details. bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer and the low part of rampz. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer and the low part of rampz. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon completion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write oper- ation if the nrww section is addressed. bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt? or pgers, the following spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer/rampz. the lsb of the z-pointer is ignored. the spmen bit will auto-clear upon completion of an spm instruction, or if no spm instruction is exe- cuted within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. addressing the flash during self- programming the z-pointer together with rampz are used to address the spm commands. for details on how to use the rampz, see ?ram page z select register ? rampz? on page 12. since the flash is organized in pages (see table 131 on page 330), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addressing the word s within a page, while the most significant bits are addressing the pages. this is shown in figure 155. note that the page erase and page write operations are addressed independently. therefore it is of major impor- tance that the boot loader software addresses the same page in both the page erase and page write operation. once a programming operation is initiated, the address is latched and the z-pointer/rampz can be used for other operations. the only spm operation that does not use the z-pointer/rampz is setting the boot loader lock bits. the content of the z-pointer/rampz is ignored and will have no effect on the operation. the (e)lpm instruction does also use the z-pointer/rampz to store bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 318 at90can128 4250e?can?12/04 the address. since this instruction addresses the flash byte by byte, also the lsb (bit z0) of the z-pointer is used. figure 155. addressing the flash during spm (1) note: 1. the different variables used in figure 155 are listed in table 121 on page 324. self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1 : fill the buffer before a page erase fill temporary page buffer perform a page erase perform a page write alternative 2 : fill the buffer after page erase perform a page erase fill temporary page buffer perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both program memory 0 1 15 1 7 0 15 z - register 0 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword [pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb rampz - register pagemsb program counter 319 at90can128 4250e?can?12/04 the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 321 for an assembly code example. performing page erase by spm to execute page erase, set up the address in the z-pointer/rampz, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register and rampz. other bits in the z-pointer must be written zero during this operation. page erase to the rww section: the nrww section can be read during the page erase. page erase to the nrww section: the cpu is halted during the operation. filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer/rampz and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write opera- tion or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. performing a page write to execute page write, set up the address in the z-pointer/rampz, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer will be ignored during this operation. page write to the rww section: the nrww section can be read during the page write. page write to the nrww section: the cpu is halted during the operation. using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 56. consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. prevent reading the rww section during self- programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?interrupts? on page 56, or the inter- rupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 321 for an example. 320 at90can128 4250e?can?12/04 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that may prevent the application and boot loader section from any software update by the mcu. see table 115 and table 116 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lock bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eewe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destina- tion register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 126 on page 327 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be loaded in the destination register as shown below. refer to table 125 on page 326 for detailed description and mapping of the fuse high byte. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 76543210 rd (z=0x0001) ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd (z=0x0000) flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd (z=0x0003) fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 321 at90can128 4250e?can?12/04 when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the destina- tion register as shown below. refer to table 124 on page 326 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply volt- age is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effec- tively protecting the spmcsr register and thus the flash from unintentional writes. programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 118 shows the typi- cal programming time for flash accesses from the cpu. simple assembly code example for a boot loader ;- the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y-pointer ; the first data location in flash is pointed to by the z-pointer ;- error handling is not included ;- the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), bit 76543210 rd (z=0x0002) ? ? ? ? efb3 efb2 efb1 efb0 table 118. spm programming time symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 322 at90can128 4250e?can?12/04 ; loophi (r25), spmcsrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;- it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcsrval, (1< 325 at90can128 4250e?can?12/04 memory programming program and data memory lock bits the at90can128 provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 123. the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed table 122. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 123. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 no restrictions for spm (store program memory) or lpm (load program memory) accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 326 at90can128 4250e?can?12/04 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed fuse bits the at90can128 has three fuse bytes. table 124, table 125 and table 126 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. see table 20 on page 50 for bodlevel fuse decoding. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 123. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 124. extended fuse byte fuse extended byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 bodlevel2 (1) 3 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 1 brown-out detector trigger level 1 (unprogrammed) ta0sel 0 (reserved for factory tests) 1 (unprogrammed) table 125. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen (5) 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) 327 at90can128 4250e?can?12/04 note: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1..0 results in maximum boot size. see table 119 on page 323 for details. 3. see ?watchdog timer control register ? wdtcr? on page 54 for details. 4. never ship a product with the ocden fuse programmed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse enables some parts of the clock system to be running in all sleep modes. this may increase the power consumption. 5. if the jtag interface is left unconnected, the jtagen fuse should if possible be dis- abled. this to avoid static current at the tdo pin in the jtag interface. note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 12 on page 39 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8 mhz. see table 5 on page 35 for details. 3. the ckout fuse allow the system clock to be output on port pc7. see ?clock out- put buffer? on page 40 for details. 4. see ?system clock prescaler? on page 41 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. bootsz1 2 select boot size (see table 119 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 119 for details) 0 (programmed) (2) bootrst 0 select reset vector 1 (unprogrammed) table 126. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) table 125. fuse high byte (continued) fuse high byte bit no description default value 328 at90can128 4250e?can?12/04 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the at90can128 the signature bytes are: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x97 (indicates 128kb flash memory). 3. 0x002: 0x81 (indicates at90can128 device when 0x001 is 0x97). calibration byte the at90can128 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this byte is automatically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. 329 at90can128 4250e?can?12/04 parallel programming overview this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90can128. pulses are assumed to be at least 250 ns unless otherwise noted. signal names in this section, some pins of the at90can128 are referenced by signal names describ- ing their functionality during parallel programming, see figure 156 and table 127. pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a posi- tive pulse. the bit coding is shown in table 129. when pulsing wr or oe , the command loaded determines the action executed. the dif- ferent commands are shown in table 130. figure 156. parallel programming pin mapping vcc +2.7 - +5.5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 dat a reset pd7 +12 v bs1 xa0 xa1 oe r dy/bsy pagel pa0 wr bs2 avcc +2.7 - +5.5v table 127. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). wr pd3 i write pulse (active low). bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte). xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte). data pb7-0 i/o bi-directional data bus (output when oe is low). 330 at90can128 4250e?can?12/04 commands parameters table 128. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 129. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 130. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 131. no. of words in a page and no. of pages in the flash flash size page size pcword no. of pages pcpage pcmsb 64k words (128k bytes) 128 words pc[6:0] 512 pc[15:7] 15 table 132. no. of words in a page and no. of pages in the eeprom eeprom size page size pcword no. of pages pcpage eeamsb 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11 331 at90can128 4250e?can?12/04 parallel programming enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 128 on page 330 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering pro- gramming mode. 5. wait at least 50 s before sending a new command. considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. the command needs only be loaded once when writing or reading multiple memory locations. skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. programming the flash the flash is organized in pages, see table 131 on page 330. when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to pro- gram the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 332 at90can128 4250e?can?12/04 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 158 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 157 on page 333. note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 158 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write sig- nals are reset. 333 at90can128 4250e?can?12/04 figure 157. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 131 on page 330. figure 158. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. programming the eeprom the eeprom is organized in pages, see table 132 on page 330. when programming the eeprom, the program data is latched in to a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 331 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). program memory 0 15 word address within a page page address within the flash instruction word pag e pcword [pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe r eset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 334 at90can128 4250e?can?12/04 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs to ?0?. 2. give wr a negative pulse. this starts programming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 159 for signal waveforms). figure 159. programming the eeprom waveforms reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 331 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. rdy/bsy wr oe r eset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 335 at90can128 4250e?can?12/04 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 331 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 331 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 331 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?program- ming the flash? on page 331 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2 to ?0?. this selects low data byte. figure 160. programming the fuses waveforms rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 336 at90can128 4250e?can?12/04 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 331 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is pro- grammed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 331 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status fo the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 161. mapping between bs1, bs2 and the fuse and lock bits during read reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 331 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 331 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. bs2 dat a 0 1 bs2 extended fuse byte fuse low byte 0 1 fuse high byte lock bits bs1 0 1 337 at90can128 4250e?can?12/04 spi serial programming overview this section describes how to serial program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90can128. signal names both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 133 on page 338, the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. note that throughout the descrip- tion about serial downloading, mosi and miso are used to describe the serial data in and serial data out respectively. for at90can128 these pins are mapped to pdi (pe0) and pdo (pe1). figure 162. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. when programming the eeprom, an auto-erase cycle is built into the self-timed pro- gramming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz vcc +2.7 - +5.5 v gnd xtal1 pb1 reset pdo pe1 pe0 pdi sck avcc +2.7 - +5.5 v 338 at90can128 4250e?can?12/04 pin mapping parameters the flash parameters are given in table 131 on page 330 and the eeprom parame- ters in table 132 on page 330. spi serial programming when writing serial data to the at90can128, data is clocked on the rising edge of sck. when reading data from the at90can128, data is clocked on the falling edge of sck. to program and verify the at90can128 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 135 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if the communication is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 9 msb of the address. if polling is not used, the user must wait at least t wd_flash before issuing the next page. (see table 134.) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory loca- tion is first automatically erased before new data is written. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 134.) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence nor- mal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. table 133. pin mapping serial programming symbol pins i/o description mosi (pdi) pe0 i serial data in miso (pdo) pe1 o serial data out sck pb1 i serial clock 339 at90can128 4250e?can?12/04 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at the time the device is ready for a new page, the programmed value will read correctly. this is used to determine when the next page can be written. note that the entire page is written simultaneously and any address within the page can be used for polling. data polling of the flash will not work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. see table 134 for t wd_flash value. data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being programmed will give the value 0xff. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to deter- mine when the next byte can be written. this will not work for the value 0xff, but the user should have the following in mind: as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re-programmed without chip erasing the device. in this case, data polling cannot be used fo r the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 134 for t wd_eeprom value. figure 163. serial programming waveforms table 134. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 9.0 ms t wd_erase 9.0 ms msb lsb lsb serial clock input (sck) serial data input (mosi-pdi) (miso-pdo) sample s erial data output msb 340 at90can128 4250e?can?12/04 table 135. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 aaaa aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx x bbb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 aaaa aaaa b xxx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x aaaa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x aaaa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . load eeprom memory page (page access) 1100 0001 0000 0000 0000 0 bbb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 00xx aaaa bbbb b000 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 122 on page 325 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 122 on page 325 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse low bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 126 on page 327 for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 125 on page 326 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx iiii set bits = ?0? to program, ?1? to unprogram. see table 124 on page 326 for details. read fuse low bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table 126 on page 327 for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro-grammed, ?1? = unprogrammed. see table 125 on page 326 for details. 341 at90can128 4250e?can?12/04 note: a = address high bits b = address low bits h = 0 - low byte, 1 - high byte o = data out i = data in x = don?t care read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro-grammed, ?1? = unprogrammed. see table 124 on page 326 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 135. serial programming instruction set (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte4 342 at90can128 4250e?can?12/04 jtag programming overview programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtagen fuse must be programmed. the device is default shipped with the fuse programmed. in addition, the jtd bit in mcucr must be cleared. alternatively, if the jtd bit is set, the external reset can be forced low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins are available for programming. this provides a means of using the jtag pins as normal port pins in running mode while still allowing in-system programming via the jtag interface. note that this technique can not be used when using the jtag pins for boundary-scan or on- chip debug. in these cases the jtag pins must be dedicated for this purpose. during programming the clock frequency of the tck input must be less than the maxi- mum frequency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficiently low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. the jtag instruc- tions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state between jtag sequences. the state machine sequence for changing the instruction word is shown in figure 164. 343 at90can128 4250e?can?12/04 figure 164. state machine sequence for changing the instruction word avr_reset (0xc) the avr specific public jtag instruction for setting the avr device in the reset mode or taking the device out from the reset mode. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?o ne? in the reset chain. the output from this chain is not latched. the active states are: shift-dr: the reset register is shifted by the tck input. prog_enable (0x4) the avr specific public jtag instruction for enabling programming via the jtag port. the 16-bit programming enable register is selected as data register. the active states are the following: shift-dr: the programming enable signature is shifted into the data register. update-dr: the programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. prog_commands (0x5) the avr specific public jtag instruction for entering programming commands via the jtag port. the 15-bit programming command register is selected as data register. the active states are the following: test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 344 at90can128 4250e?can?12/04 capture-dr: the result of the previous command is loaded into the data register. shift-dr: the data register is shifted by the tck input, shifting out the result of the previous command and shifting in the new command. update-dr: the programming command is applied to the flash inputs run-test/idle: one clock cycle is generated, executing the applied command (not always required, see table 136 below). prog_pageload (0x6) the avr specific public jtag instruction to directly load the flash data page via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: shift-dr: the flash data byte register is shifted by the tck input. update-dr: the content of the flash data byte register is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. prog_pageread (0x7) the avr specific public jtag instruction to directly capture the flash content via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. shift-dr: the flash data byte register is shifted by the tck input. data registers the data registers are selected by the jtag instruction registers described in section ?programming specific jtag instructions? on page 342. the data registers relevant for programming operations are: reset register programming enable register programming command register flash data byte register reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse settings for the clock options, the part will remain reset for a reset time-out 345 at90can128 4250e?can?12/04 period (refer to ?clock sources? on page 35) after releasing the reset register. the out- put from this data register is not latched, so the reset will take place immediately, as shown in figure 144 on page 292. programming enable register the programming enable register is a 16-bit register. the contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. when the contents of the register is equal to the program- ming enable signature, programming via the jtag port is enabled. the register is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 165. programming enable register programming command register the programming command register is a 15-bit register. this register is used to seri- ally shift in programming commands, and to serially shift out the result of the previous command, if any. the jtag programming instruction set is shown in table 136. the state sequence when shifting in the programming commands is illustrated in figure 167. tdi tdo d a t a = dq clockdr & prog_enable programming enable 0xa370 346 at90can128 4250e?can?12/04 figure 166. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits 347 at90can128 4250e?can?12/04 table 136. jtag programming instruction set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (2) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 2c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2d. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2e. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2f. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2g. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. poll for page write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 3c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3d. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. poll for page write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 348 at90can128 4250e?can?12/04 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (6) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6e. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6h. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (7) 01111 10_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8d. read fuse low byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (5) table 136. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 349 at90can128 4250e?can?12/04 notes: 1. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 124 on page 326 7. the bit mapping for fuses high byte is listed in table 125 on page 326 8. the bit mapping for fuses low byte is listed in table 126 on page 327 9. the bit mapping for lock bits byte is listed in table 122 on page 325 10. address bits exceeding pcmsb and eeamsb (table 131 and table 132) are don?t care 11. all tdi and tdo sequnces are represented by binary digits (0b...). 8f. read fuses and lock bits 0111010_00000000 01111 10_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 136. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 350 at90can128 4250e?can?12/04 figure 167. state machine sequence for changing/reading the data word flash data byte register the flash data byte register provides an efficient way to load the entire flash page buffer before executing page write, or to read out/verify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of the 8-bit scan chain and a 8-bit tempo- rary register. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update- dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first wri tten byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 351 at90can128 4250e?can?12/04 including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. figure 168. flash data byte register the state machine controlling the flash data byte register is clocked by tck. during normal operation in which eight bits are shifted for each flash byte, the clock cycles needed to navigate through the tap controller automatically feeds the state machine for the flash data byte register with sufficient number of clock pulses to complete its oper- ation transparently for the user. however, if too few bits are shifted between each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to ensure that there are at least 11 tck cycles between each update-dr state. programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 136. entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the pro- gramming enable register. leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the programming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase complete using programming instruction 1b, or wait for t wlrh_ce (refer to table 150 on page 372). tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine 352 at90can128 4250e?can?12/04 programming the flash 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address high byte using programming instruction 2b. 4. load address low byte using programming instruction 2c. 5. load data using programming instructions 2d, 2e and 2f. 6. repeat steps 4 and 5 for all instruction words in the page. 7. write the page using programming instruction 2g. 8. poll for flash write complete using programming instruction 2h, or wait for t wlrh (refer to ). 9. repeat steps 3 to 7 until all data have been programmed. a more efficient data transfer can be achieved using the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b and 2c. pcword (refer to table 131 on page 330) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte register into the flash page location and to auto-increment the program counter before each new word. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2g. 8. poll for flash write complete using programming instruction 2h, or wait for t wlrh (refer to table 150 on page 372). 9. repeat steps 3 to 8 until all data have been programmed. reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b and 3c. 4. read data using programming instruction 3d. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be achieved using the prog_pageread instruction: 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b and 3c. pcword (refer to table 131 on page 330) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first instruction in the page (flash) and ending with the msb of the last instruction in the page (flash). the capture-dr state both captures the data from the flash, and also auto-increments the pro- 353 at90can128 4250e?can?12/04 gram counter after each word is read. note that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been read. programming the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom write using programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. write the data using programming instruction 4f. 8. poll for eeprom write complete using programming instruction 4g, or wait for t wlrh (refer to table 150 on page 372). 9. repeat steps 3 to 8 until all data have been programmed. note that the prog_pageload instruction can not be used when programming the eeprom. reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. note that the prog_pageread instruction can not be used when reading the eeprom. programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6a. 3. load data high byte using programming instructions 6b. a bit value of ?0? will program the corresponding fuse, a ?1? will unprogram the fuse. 4. write fuse high byte using programming instruction 6c. 5. poll for fuse write complete using programming instruction 6d, or wait for t wlrh (refer to table 150 on page 372). 6. load data low byte using programming instructions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. write fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming instruction 6g, or wait for t wlrh (refer to table 150 on page 372). programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write using programming instruction 7a. 3. load data using programming instructions 7b. a bit value of ?0? will program the corresponding lock bit, a ?1? will leave the lock bit unchanged. 4. write lock bits using programming instruction 7c. 5. poll for lock bit write complete using programming instruction 7d, or wait for t wlrh (refer to table 150 on page 372). 354 at90can128 4250e?can?12/04 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8f. to only read extended fuse byte, use programming instruction 8b. to only read fuse high byte, use programming instruction 8c. to only read fuse low byte, use programming instruction 8d. to only read lock bits, use programming instruction 8e. reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 355 at90can128 4250e?can?12/04 electrical characteristics (1) absolute maximum ratings* note: 1. electrical characteristics for this product have not yet been finalized. please consider all values listed herein as preliminary and non-contractual. industrial operating temperature ...................? 40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ....................................? 65c to +150c voltage on any pin except reset with respect to ground .............................. ? 0.5v to v cc +0.5v voltage on reset with respect to ground.... ? 0.5v to +13.0v voltage on v cc with respect to ground............. ? 0.5v to 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma 356 at90can128 4250e?can?12/04 dc characteristics ta = -40 c to +85 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage except xtal1 and reset pins ? 0.5 0.2 vcc (1) v v il1 input low voltage xtal1 pin - external clock selected ? 0.5 0.1 vcc (1) v v il2 input low voltage reset pin ? 0.5 0.2 vcc (1) v v ih input high voltage except xtal1 and reset pins 0.6 vcc (2) vcc + 0.5 v v ih1 input high voltage xtal1 pin - external clock selected 0.7 vcc (2) vcc + 0.5 v v ih2 input high voltage reset pin 0.85 vcc (2) vcc + 0.5 v v ol output low voltage (3) (ports a, b, c, d, e, f, g) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v oh output high voltage (4) (ports a, b, c, d, e, f, g) i oh = ? 20 ma, v cc = 5v i oh = ? 10 ma, v cc = 3v 4.2 2.4 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1.0 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1.0 a r rst reset pull-up resistor 30 60 k ? r pu i/o pin pull-up resistor 30 60 k ? i cc power supply current active mode 8 mhz, v cc = 5v 20 ma 16 mhz, v cc = 5v 32 ma 4 mhz, v cc = 3v 5 ma 8 mhz, v cc = 3v 9 ma power supply current idle mode 8 mhz, v cc = 5v 12 ma 16 mhz, v cc = 5v 21 ma 4 mhz, v cc = 3v 2 ma 8 mhz, v cc = 3v 7.5 ma power supply current power-down mode wdt enabled, v cc = 5v 25 a wdt disabled, v cc = 5v 3.5 a wdt enabled, v cc = 3v 8 a wdt disabled, v cc = 3v 1 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 1.0 8.0 20 mv 357 at90can128 4250e?can?12/04 note: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where the pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: tqfp and qfn package: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for ports a0 - a7, g2, c3 - c7 should not exceed 300 ma. 3] the sum of all iol, for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 150 ma. 4] the sum of all iol, for ports b0 - b7, g3 - g4, e0 - e7 should not exceed 150 ma. 5] the sum of all iol, for ports f0 - f7, should not exceed 200 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (-20 ma at v cc = 5v, -10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: tqfp and qfn package: 1] the sum of all i oh , for all ports, should not exceed -400 ma. 2] the sum of all i oh , for ports a0 - a7, g2, c3 - c7 should not exceed -300 ma. 3] the sum of all i oh , for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 1-50 ma. 4] the sum of all i oh , for ports b0 - b7, g3 - g4, e0 - e7 should not exceed -150 ma. 5] the sum of all i oh , for ports f0 - f7, should not exceed -200 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 ? 50 50 na t acid analog comparator propagation delay common mode vcc/2 v cc = 2.7v 170 ns v cc = 5.0v 180 ns ta = -40 c to +85 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units 358 at90can128 4250e?can?12/04 external clock drive characteristics figure 169. external clock drive waveforms table 137. external clock drive symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 50 25 ns t clcx low time 50 25 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s ? t clcl change in period from one clock cycle to the next 22% v il1 v ih1 359 at90can128 4250e?can?12/04 two-wire serial interface characteristics table 138 describes the requirements for devices connected to the two-wire serial bus. the at90can128 two-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 170. table 138. two-wire serial bus requirements symbol parameter condition min max units v il input low-voltage ? 0.5 0.3 vcc v v ih input high-voltage 0.7 vcc vcc + 0.5 v v hys (1) hysteresis of schmitt trigger inputs 0.05 vcc (2) ?v v ol (1) output low-voltage 3 ma sink current 0 0.4 v t r (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns t of (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns t sp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1 v cc < v i < 0.9 v cc ? 10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t low low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- ? v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - ? 360 at90can128 4250e?can?12/04 notes: 1. in at90can128, this parameter is characterized and not 100% tested. 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all at90can128 two-wire serial interface operation. other devices connected to the two-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the at90can128 two-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the at90can128 two-wire serial interface is (1/f scl - 2/f ck ), thus the low time require- ment will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, at90can128 devices connected to the bus may communicate at full speed (400 khz) with other at90can128 devices, as well as any other device with a proper t low accep- tance margin. figure 170. two-wire serial bus timing t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s table 138. two-wire serial bus requirements (continued) symbol parameter condition min max units t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf s cl s da t r 361 at90can128 4250e?can?12/04 spi timing characteristics see figure 171 and figure 172 for details. notes: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck >12 mhz figure 171. spi interface timing requirements (master mode) table 139. spi timing parameters description mode min. typ. max. 1 sck period master see table 74 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5holdmaster 10 6 out to sck master 0.5 t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 t ck 11 sck high/low (1) slave 2 t ck 12 rise/fall time slave 1.6 s 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 t ck mo si ( data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 362 at90can128 4250e?can?12/04 figure 172. spi interface timing requirements (slave mode) can physical layer characteristics only pads dedicated to the can communication belong to the physical layer. notes: 1. characteristics for can physical layer have not yet been finalized. 2. metastable immunity flip-flop. mi so ( data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 18 table : can physical layer characteristics (1) parameter condition min. max. units 1 txcan output delay vcc=2.7 v load=20 pf v ol /v oh =v cc / 2 9 ns vcc=4.5 v load=20 pf v ol /v oh =v cc / 2 5.3 2 rxcan input delay vcc=2.7 v v il /v ih =v cc / 2 9 + 1 / f clk io (2) vcc=4.5 v v il /v ih =v cc / 2 7.2 + 1 / f clk io (2) 363 at90can128 4250e?can?12/04 adc characteristics note: 1. values are guidelines only. 2. minimum for av cc is 2.7 v. 3. maximum for av cc is 5.5 v table 140. adc characteristics, single ended channels symbol parameter condition min (1) typ (1) max (1) units resolution single ended conversion 10 bits absolute accuracy (included inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 1.5 lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 1 mhz lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz noise reduction mode 1.5 lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 1 mhz noise reduction mode lsb integral non-linearity (inl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.5 1 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.3 1 lsb gain error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 2 0 + 2 lsb offset error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 2 1 + 2 lsb clock frequency free running conversion 50 1000 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (2) v cc + 0.3 (3) v v ref external reference voltage 2.0 av cc v v in input voltage gnd v ref v input bandwidth 38.5 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 32 k ? r ain analog input resistance 100 m ? 364 at90can128 4250e?can?12/04 note: 1. values are guidelines only. 2. minimum for av cc is 2.7 v. 3. maximum for av cc is 5.5 v table 141. adc characteristics, differential channels symbol parameter condition min (1) typ (1) max (1) units resolution differential conversion gain = 1x or 10x 8bits differential conversion gain = 200x 7bits absolute accuracy gain = 1x , 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 1lsb integral non-linearity (inl) (accuracy after calibration for offset and gain error) gain = 1x , 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 0.5 1 lsb gain error gain = 1x , 10x or 200x ? 2 0 + 2 lsb offset error gain = 1x , 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz ? 1 0 + 1 lsb clock frequency free running conversion 50 200 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (2) v cc + 0.3 (3) v v ref external reference voltage differential conversion 2.0 av cc - 0.5 v v in input voltage differential conversion 0 av cc v v diff input differential voltage ?v ref /gain +v ref /gain v adc convertion output ?511 511 lsb input bandwidth differential conversion 4 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 32 k ? r ain analog input resistance 100 m ? 365 at90can128 4250e?can?12/04 external data memory characteristics notes: 1. this assumes 50% clock duty cycle. the half period is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half period is actually the low time of the external clock, xtal1. table 142. external data memory characteristics, v cc = 4.5 - 5.5 volts, no wait-state symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 115 1.0 t clcl ? 10 ns 2t avll address valid a to ale low 57.5 0.5 t clcl ? 5 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 57.5 0.5 t clcl ? 5 (1) ns 5t avrl address valid to rd low 115 1.0 t clcl ? 10 ns 6t avwl address valid to wr low 115 1.0 t clcl ? 10 ns 7t llwl ale low to wr low 47.5 67.5 0.5 t clcl ? 15 (2) 0.5 t clcl + 5 (2) ns 8t llrl ale low to rd low 47.5 67.5 0.5 t clcl ? 15 (2) 0.5 t clcl + 5 (2) ns 9t dvrh data setup to rd high 40 40 ns 10 t rldv read low to data valid 75 1.0 t clcl ? 50 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 115 1.0 t clcl ? 10 ns 13 t dvwl data setup to wr low 42.5 0.5 t clcl ? 20 (1) ns 14 t whdx data hold after wr high 115 1.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 125 1.0 t clcl ns 16 t wlwh wr pulse width 115 1.0 t clcl ? 10 ns 366 at90can128 4250e?can?12/04 table 143. external data memory characteristics, v cc = 4.5 - 5.5 volts, 1 cycle wait-state symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 2.0 t clcl ? 50 ns 12 t rlrh rd pulse width 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 240 2.0 t clcl ns 16 t wlwh wr pulse width 240 2.0 t clcl ? 10 ns table 144. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 0 symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns table 145. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 1 symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 14 t whdx data hold after wr high 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns 367 at90can128 4250e?can?12/04 notes: 1. this assumes 50% clock duty cycle. the half period is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half period is actually the low time of the external clock, xtal1. table 146. external data memory characteristics, v cc = 2.7 - 5.5 volts, no wait-state symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 235 t clcl ? 15 ns 2t avll address valid a to ale low 115 0.5 t clcl ? 10 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 115 0.5 t clcl ? 10 (1) ns 5t avrl address valid to rd low 235 1.0 t clcl ? 15 ns 6t avwl address valid to wr low 235 1.0 t clcl ? 15 ns 7t llwl ale low to wr low 115 130 0.5 t clcl ? 10 (2) 0.5 t clcl + 5 (2) ns 8t llrl ale low to rd low 115 130 0.5 t clcl ? 10 (2) 0.5 t clcl + 5 (2) ns 9t dvrh data setup to rd high 45 45 ns 10 t rldv read low to data valid 190 1.0 t clcl ? 60 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 235 1.0 t clcl ? 15 ns 13 t dvwl data setup to wr low 105 0.5 t clcl ? 20 (1) ns 14 t whdx data hold after wr high 235 1.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 250 1.0 t clcl ns 16 t wlwh wr pulse width 235 1.0 t clcl ? 15 ns 368 at90can128 4250e?can?12/04 table 147. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 0, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 440 2.0 t clcl ? 60 ns 12 t rlrh rd pulse width 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 500 2.0 t clcl ns 16 t wlwh wr pulse width 485 2.0 t clcl ? 15 ns table 148. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns table 149. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 14 t whdx data hold after wr high 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns 369 at90can128 4250e?can?12/04 figure 173. external memory timing (srwn1 = 0, srwn0 = 0) figure 174. external memory timing (srwn1 = 0, srwn0 = 1) ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address s ystem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address s ystem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 370 at90can128 4250e?can?12/04 figure 175. external memory timing (srwn1 = 1, srwn0 = 0) figure 176. external memory timing (srwn1 = 1, srwn0 = 1) (1) note: 1. the ale pulse in the last period (t4-t7) is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address s ystem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address s ystem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 t6 371 at90can128 4250e?can?12/04 parallel programming characteristics figure 177. parallel programming timing, including some general timing requirements figure 178. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 177 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. data & contol ( data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 p agel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) 372 at90can128 4250e?can?12/04 figure 179. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 177 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. x tal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz table 150. parallel programming characteristics, v cc = 5v 10% symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 10 ms t xlol xtal1 low to oe low 0 ns 373 at90can128 4250e?can?12/04 notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 150. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min. typ. max. units 374 at90can128 4250e?can?12/04 at90can128 typical characteristics the following charts show typical behavior. these figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. active supply current figure 180. active supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. frequency (0.1 - 1 mhz) 0 0.5 1 1.5 2 2.5 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 375 at90can128 4250e?can?12/04 figure 181. active supply current vs. frequency (1 - 16 mhz) figure 182. active supply current vs. vcc (internal rc oscillator 8 mhz) active supply current vs. frequency (1 - 16 mhz) 0 5 10 15 20 25 30 35 40 45 50 01234567891011121314151617 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v active supply current vs. vcc (internal rc oscillator 8 mhz) 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c 376 at90can128 4250e?can?12/04 figure 183. active supply current vs. vcc (internal rc oscillator 1 mhz) figure 184. active supply current vs. vcc (32 khz watch crystal) active supply current vs. vcc (internal rc oscillator 1 mhz) 0 0.5 1 1.5 2 2.5 3 3.5 2.533.544.555.5 vcc (v) icc (ma) 85c 25c -40c active supply current vs. vcc (32 khz watch crystal) 0 20 40 60 80 100 120 140 2.533.544.555.5 vcc (v) icc (ua) 25c will be updated later 377 at90can128 4250e?can?12/04 idle supply current figure 185. idle supply current vs. frequency (0.1 - 1.0 mhz) figure 186. idle supply current vs. frequency (1 - 16 mhz) idle supply current vs. frequency (0.1 - 1 mhz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v idle supply current vs. frequency (1 - 16 mhz) 0 5 10 15 20 25 30 01234567891011121314151617 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 378 at90can128 4250e?can?12/04 figure 187. idle supply current vs. vcc (internal rc oscillator 8 mhz) figure 188. idle supply current vs. vcc (internal rc oscillator 1 mhz) idle supply current vs. vcc (internal rc oscillator 8 mhz) 0 2 4 6 8 10 12 14 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c idle supply current vs. vcc (internal rc oscillator 1 mhz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.533.544.555.5 vcc (v) icc (ma) 85c 25c -40c 379 at90can128 4250e?can?12/04 figure 189. idle supply current vs. vcc (32 khz watch crystal) power-down supply current figure 190. power-down supply current vs. vcc (watchdog timer disabled) idle supply current vs. vcc (32 khz watch crystal) 0 10 20 30 40 50 60 2.533.544.555.5 vcc (v) icc (ua) 25c power-down supply current vs. vcc (watchdog timer disabled) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c will be updated later 380 at90can128 4250e?can?12/04 figure 191. power-down supply current vs. vcc (watchdog timer enabled) power-save supply current figure 192. power-save supply current vs. vcc (watchdog timer disabled) power-down supply current vs. vcc (watchdog timer enabled) 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c will be updated later power-save supply current vs. vcc (watchdog timer disabled) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c will be updated later 381 at90can128 4250e?can?12/04 standby supply current figure 193. power-save supply current vs. vcc (25c, watchdog timer disabled) pin pull-up figure 194. i/o pin pull-up resistor current vs. input voltage (vcc = 5v) standby supply current vs. vcc (25c, watchdog timer disabled) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 2.533.544.555.5 vcc (v) icc (ma) 6 mhz xtal 4 mhz res 2 mhz xtal 2 mhz res will be updated later i/o pin pull-up resistor current vs. input voltage (vcc = 5v) -160 -140 -120 -100 -80 -60 -40 -20 0 0123456 v io (v) i io (ua) 85c 25c -40c 382 at90can128 4250e?can?12/04 figure 195. i/o pin pull-up resistor current vs. input voltage (vcc = 2.7v) figure 196. reset pull-up resistor current vs. reset pin voltage (vcc = 5v) i/o pin pull-up resistor current vs. input voltage (vcc = 2.7v) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 00.5 11.522.53 v io (v) i io (ua) 85c 25c -40c reset pull-up resistor current vs. reset pin voltage (vcc = 5v) -120 -100 -80 -60 -40 -20 0 0123456 v reset (v) i reset (ua) 85c 25c -40c 383 at90can128 4250e?can?12/04 figure 197. reset pull-up resistor current vs. reset pin voltage (vcc = 2.7v) pin driver strength figure 198. i/o pin source current vs. output voltage (vcc = 5v) reset pull-up resistor c urrent vs. r eset pin voltage (vcc = 2.7v) -70 -60 -50 -40 -30 -20 -10 0 00.5 11.522.53 v reset (v) i reset (ua) 85c 25c -40c i/o pin source current vs. output voltage (vcc = 5v) -25 -20 -15 -10 -5 0 2.5 3 3.5 4 4.5 5 v oh (v) i oh (ma) 85c 25c -40c measurements clamped at -20 ma by tester 384 at90can128 4250e?can?12/04 figure 199. i/o pin source current vs. output voltage (vcc = 2.7v) figure 200. i/o pin sink current vs. output voltage (vcc = 5v) i/o pin source current vs. output voltage (vcc = 2.7v) -25 -20 -15 -10 -5 0 00.5 11.522.53 v oh (v) i oh (ma) 85c 25c -40c measurements clamped at -20 ma by tester i/o pin sink current vs. output voltage (vcc = 5v) 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v ol (v) i ol (ma) 85c 25c -40c measurements clamped at 20 ma by tester 385 at90can128 4250e?can?12/04 figure 201. i/o pin sink current vs. output voltage (vcc = 2.7v) bod thresholds and analog comparator offset figure 202. bod thresholds vs. temperature (bod level is 4.1v) i/o pin sink current vs. output voltage (vcc = 2.7v) 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v ol (v) i ol (ma) 85c 25c -40c measurements clamped at 20 ma by tester bod thresholds vs. temperature (bod level is 4.1v) 3.4 3.6 3.8 4 4.2 4.4 -60 -40 -20 0 20 40 60 80 100 temp (c) threshold (v) rising vcc falling vcc 386 at90can128 4250e?can?12/04 figure 203. bod thresholds vs. temperature (bod level is 2.7v) figure 204. bandgap voltage vs. operating voltage bod thresholds vs. temperature (bod level is 2.7v) 2 2.2 2.4 2.6 2.8 3 -60 -40 -20 0 20 40 60 80 100 temp (c) threshold (v) rising vcc falling vcc bandgap voltage vs. operating voltage 1.08 1.09 1.1 1.11 1.12 1.13 1.14 2.533.544.555.5 vcc (v) bandgap voltage (v) 85c 25c -40c 387 at90can128 4250e?can?12/04 figure 205. analog comparator offset vs. common mode voltage (vcc = 5v) internal oscillator speed figure 206. watchdog oscillator frequency vs. operating voltage analog comparator offset vs. common mode voltage (vcc = 5v) -0.002 0 0.002 0.004 0.006 0.008 0.01 0.012 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 common voltage mode (v) comparator offset voltage (v) 85c 25c -40c watchdog oscillator frequency vs. vcc 800 850 900 950 1000 1050 1100 1150 1200 2.533.544.555.5 vcc (v) f watchdog (khz) 85c 25c 25c 388 at90can128 4250e?can?12/04 figure 207. calibrated 8 mhz rc oscillator frequency vs. temperature figure 208. calibrated 8 mhz rc oscillator frequency vs. operating voltage calibrated 8mhz rc oscillator frequency vs. temperature 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 -60 -40 -20 0 20 40 60 80 100 temp (c) f rc (mhz) 2.7v 4.0v 5.5v will be updated later (- 40c) calibrated 8mhz rc oscillator frequency vs. vcc 6 6.5 7 7.5 8 8.5 9 9.5 10 2.5 3 3.5 4 4.5 5 5.5 vcc (v) f rc (mhz) 85c 25c will be updated later (- 40c) 389 at90can128 4250e?can?12/04 figure 209. calibrated 8 mhz rc oscillator frequency vs. osccal value current consumption of peripheral units figure 210. brownout detector current vs. operating voltage calibrated 8mhz rc oscillator frequency vs. osccal value 4 5 6 7 8 9 10 11 12 13 14 15 16 0 163248648096112128 osccal value f rc (mhz) 85c 25c will be updated later (- 40c) brownout detector current vs. vcc 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c 390 at90can128 4250e?can?12/04 figure 211. adc current vs. operating voltage (adc at 1 mhz) figure 212. aref external reference current vs. operating voltage adc current vs. vcc (adc at 1 mhz) 0 50 100 150 200 250 300 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c aref external reference current vs. vcc 40 60 80 100 120 140 160 180 200 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i aref (ua) 85c 25c -40c 391 at90can128 4250e?can?12/04 figure 213. analog comparator current vs. operating voltage figure 214. programming current vs. operating voltage analog comparator current vs. vcc 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i cc (ua) 85c 25c -40c programming current vs. vcc 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i cc (ma) 85c 25c -40c 392 at90can128 4250e?can?12/04 current consumption in reset and reset pulse width figure 215. reset supply current vs. operating voltage (0.1 - 1.0 mhz) (excluding current through the reset pull-up) figure 216. reset supply current vs. operating voltage (1 - 16 mhz) (excluding current through the reset pull-up) reset supply c urrent vs. frequency (0.1 - 1 mhz) ( excluding current through the reset pull- up) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v reset supply current vs. frequency (1 - 16 mhz) (excluding current through the reset pull-up) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 393 at90can128 4250e?can?12/04 figure 217. minimum reset pulse width vs. operating voltage minimum reset pulse width vs. vcc 0 250 500 750 1000 1250 1500 2.5 3 3.5 4 4.5 5 5.5 vcc (v) pulse width (ns) 85c 25c -40c 394 at90can128 4250e?can?12/04 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) canmsg msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 page 259 (0xf9) canstmh timstm15 timstm14 timstm13 timstm12 timstm11 timstm10 timstm9 timstm8 page 259 (0xf8) canstml timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 timstm0 page 259 (0xf7) canidm1 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 page 258 (0xf6) canidm2 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 page 258 (0xf5) canidm3 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 page 258 (0xf4) canidm4 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0rtrmsk ? idemsk page 258 (0xf3) canidt1 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 page 257 (0xf2) canidt2 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 page 257 (0xf1) canidt3 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 page 257 (0xf0) canidt4 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag page 257 (0xef) cancdmob conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 page 256 (0xee) canstmob dlcw txok rxok berr serr cerr ferr aerr page 254 (0xed) canpage mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 page 254 (0xec) canhpmob hpmob3 hpmob2 hpmob1 hpmob0 cgp3 cgp2 cgp1 cgp0 page 254 (0xeb) canrec rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 page 253 (0xea) cantec tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 page 253 (0xe9) canttch timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 timttc9 timttc8 page 253 (0xe8) canttcl timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 timttc0 page 253 (0xe7) cantimh cantim15 cantim14 cantim13 cantim12 ca ntim11 cantim10 cantim9 cantim8 page 253 (0xe6) cantiml cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 cantim0 page 253 (0xe5) cantcon tprsc7 tprsc6 tprsc5 tprsc4 tprs c3 tprsc2 trpsc1 tprsc0 page 252 (0xe4) canbt3 ? phs22 phs21 phs20 phs12 phs11 phs10 smp page 252 (0xe3) canbt2 ? sjw1 sjw0 ? prs2 prs1 prs0 ? page 251 (0xe2) canbt1 ? brp5 brp4 brp3 brp2 brp1 brp0 ? page 251 (0xe1) cansit1 ? sit14 sit13 sit12 sit11 sit10 sit9 sit8 page 250 (0xe0) cansit2 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 page 250 (0xdf) canie1 ? iemob14 iemob13 iemob12 iemob11 iemob10 iemob9 iemob8 page 250 (0xde) canie2 iemob7 iemob6 iemob5 iemob4 iemob3 iemob2 iemob1 iemob0 page 250 (0xdd) canen1 ? enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 page 250 (0xdc) canen2 enmob7 enmob6 enmob5 enmob4 enmo b3 enmob2 enmob1 enmob0 page 250 (0xdb) cangie enit enboff enrx entx enerr enbx energ enovrt page 249 (0xda) cangit canit boffit ovrtim bxok serg cerg ferg aerg page 248 (0xd9) cangsta ?ovrg ? txbsy rxbsy enfg boff errp page 247 (0xd8) cangcon abrq ovrq ttc synttc listen test ena/stb swres page 246 (0xd7) reserved (0xd6) reserved (0xd5) reserved (0xd4) reserved (0xd3) reserved (0xd2) reserved (0xd1) reserved (0xd0) reserved (0xcf) reserved (0xce) udr1 udr17 udr16 udr15 udr14 udr13 udr12 udr11 udr10 page 189 (0xcd) ubrr1h ? ? ? ? ubrr111 ubrr110 ubrr19 ubrr18 page 193 (0xcc) ubrr1l ubrr17 ubrr16 ubrr15 ubrr14 ubrr13 ubrr12 ubrr11 ubrr10 page 193 (0xcb) reserved (0xca) ucsr1c ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 page 192 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 page 191 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 page 189 (0xc7) reserved (0xc6) udr0 udr07 udr06 udr05 udr04 udr03 udr02 udr01 udr00 page 189 (0xc5) ubrr0h ? ? ? ? ubrr011 ubrr010 ubrr09 ubrr08 page 193 (0xc4) ubrr0l ubrr07 ubrr06 ubrr05 ubrr04 ubrr03 ubrr02 ubrr01 ubrr00 page 193 (0xc3) reserved (0xc2) ucsr0c ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 page 191 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 page 190 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 189 395 at90can128 4250e?can?12/04 (0xbf) reserved (0xbe) reserved (0xbd) reserved (0xbc) twcr twint twea twsta twsto twwc twen ? twie page 207 (0xbb) twdr twdr7 twdr6 twdr5 twdr4 twdr3 twdr2 twdr1 twdr0 page 209 (0xba) twar twar6 twar5 twar4 twar3 twar2 twar1 twar0 twgce page 209 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 page 208 (0xb8) twbr twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 page 207 (0xb7) reserved (0xb6) assr ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub page 154 (0xb5) reserved (0xb4) reserved (0xb3) ocr2a ocr2a7 ocr2a6 ocr2a5 ocr2a4 ocr2 a3 ocr2a2 ocr2a1 ocr2a0 page 154 (0xb2) tcnt2 tcnt27 tcnt26 tcnt25 tcnt24 tcnt 23 tcnt22 tcnt21 tcnt20 page 153 (0xb1) reserved (0xb0) tccr2a foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 page 159 (0xaf) reserved (0xae) reserved (0xad) reserved (0xac) reserved (0xab) reserved (0xaa) reserved (0xa9) reserved (0xa8) reserved (0xa7) reserved (0xa6) reserved (0xa5) reserved (0xa4) reserved (0xa3) reserved (0xa2) reserved (0xa1) reserved (0xa0) reserved (0x9f) reserved (0x9e) reserved (0x9d) ocr3ch ocr3c15 ocr3c14 ocr3c13 ocr3c12 ocr3c11 ocr3c10 ocr3c9 ocr3c8 page 136 (0x9c) ocr3cl ocr3c7 ocr3c6 ocr3c5 ocr3c4 ocr3 c3 ocr3c2 ocr3c1 ocr3c0 page 136 (0x9b) ocr3bh ocr3b15 ocr3b14 ocr3b13 ocr3b12 ocr3b11 ocr3b10 ocr3b9 ocr3b8 page 136 (0x9a) ocr3bl ocr3b7 ocr3b6 ocr3b5 ocr3b4 ocr3 b3 ocr3b2 ocr3b1 ocr3b0 page 136 (0x99) ocr3ah ocr3a15 ocr3a14 ocr3a13 ocr3a12 ocr3a11 ocr3a10 ocr3a9 ocr3a8 page 136 (0x98) ocr3al ocr3a7 ocr3a6 ocr3a5 ocr3a4 ocr3 a3 ocr3a2 ocr3a1 ocr3a0 page 136 (0x97) icr3h icr315 icr314 icr313 icr312 icr311 icr310 icr39 icr38 page 137 (0x96) icr3l icr37 icr36 icr35 icr34 icr33 icr32 icr31 icr30 page 137 (0x95) tcnt3h tcnt315 tcnt314 tcnt313 tcnt312 tcnt311 tcnt310 tcnt39 tcnt38 page 135 (0x94) tcnt3l tcnt37 tcnt36 tcnt35 tcnt34 tcnt 33 tcnt32 tcnt31 tcnt30 page 135 (0x93) reserved (0x92) tccr3c foc3a foc3b foc3c ? ? ? ? page 135 (0x91) tccr3b icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 page 133 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 page 131 (0x8f) reserved (0x8e) reserved (0x8d) ocr1ch ocr1c15 ocr1c14 ocr1c13 ocr1c12 ocr1c11 ocr1c10 ocr1c9 ocr1c8 page 136 (0x8c) ocr1cl ocr1c7 ocr1c6 ocr1c5 ocr1c4 ocr1 c3 ocr1c2 ocr1c1 ocr1c0 page 136 (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr1b8 page 136 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1 b3 ocr1b2 ocr1b1 ocr1b0 page 136 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr1a8 page 136 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1 a3 ocr1a2 ocr1a1 ocr1a0 page 136 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 page 136 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 page 136 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 page 135 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt 13 tcnt12 tcnt11 tcnt10 page 135 (0x83) reserved (0x82) tccr1c foc1a foc1b foc1c ? ? ? ? ? page 134 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 133 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 page 131 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d page 264 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 283 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 396 at90can128 4250e?can?12/04 (0x7d) reserved (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 279 (0x7b) adcsrb adhsm acme ? ? ? adts2 adts1 adts0 page 283, 262 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 281 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 page 282 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / page 282 (0x77) reserved (0x76) reserved (0x75) xmcrb xmbk ? ? ? ? xmm2 xmm1 xmm0 page 30 (0x74) xmcra sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 page 28 (0x73) reserved (0x72) reserved (0x71) timsk3 ? ?icie3 ? ocie3c ocie3b ocie3a toie3 page 137 (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 page 156 (0x6f) timsk1 ? ?icie1 ? ocie1c ocie1b ocie1a toie1 page 137 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 page 107 (0x6d) reserved (0x6c) reserved (0x6b) reserved (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 89 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 88 (0x68) reserved (0x67) reserved (0x66) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 page 39 (0x65) reserved (0x64) reserved (0x63) reserved (0x62) reserved (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 41 (0x60) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 page 54 0x3f (0x5f) sreg i t h s v n z c page 10 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 12 0x3c (0x5c) reserved 0x3b (0x5b) rampz ? ? ? ? ? ? ? rampz0 page 12 0x3a (0x5a) reserved 0x39 (0x59) reserved 0x38 (0x58) reserved 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen page 316 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd ? ?pud ? ? ivsel ivce page 59, 68, 293 0x34 (0x54) mcusr ? ? ? jtrf wdrf borf extrf porf page 51, 294 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se page 43 0x32 (0x52) reserved 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 page 288 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 page 262 0x2f (0x4f) reserved 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 page 169 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x page 168 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 167 0x2b (0x4b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior 23 gpior22 gpior21 gpior20 page 33 0x2a (0x4a) gpior1 gpior17 gpior16 gpior15 gpior14 gpior 13 gpior12 gpior11 gpior10 page 33 0x29 (0x49) reserved 0x28 (0x48) reserved 0x27 (0x47) ocr0a ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0 a3 ocr0a2 ocr0a1 ocr0a0 page 107 0x26 (0x46) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt 03 tcnt02 tcnt01 tcnt00 page 106 0x25 (0x45) reserved 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 page 104 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr310 page 92, 159 0x22 (0x42) eearh ? ? ? ? eear11 eear10 eear9 eear8 page 19 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 19 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 page 19 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere page 20 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior 03 gpior02 gpior01 gpior00 page 33 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 page 90 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 page 90 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 397 at90can128 4250e?can?12/04 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the at90can128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) reserved 0x1a (0x3a) reserved 0x19 (0x39) reserved 0x18 (0x38) tifr3 ? ?icf3 ? ocf3c ocf3b ocf3a tov3 page 138 0x17 (0x37) tifr2 ? ? ? ? ? ? ocf2a tov2 page 157 0x16 (0x36) tifr1 ? ?icf1 ? ocf1c ocf1b ocf1a tov1 page 138 0x15 (0x35) tifr0 ? ? ? ? ? ? ocf0a tov0 page 107 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 page 87 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 page 87 0x12 (0x32) ping ? ? ? ping4 ping3 ping2 ping1 ping0 page 87 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 page 86 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 page 86 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 page 87 0x0e (0x2e) porte porte7 porte6 porte5 porte4 port e3 porte2 porte1 porte0 page 86 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 86 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 page 86 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 86 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 86 0x09 (0x29) pind pind7 pind6 pind5 pi nd4 pind3 pind2 pind1 pind0 page 86 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 85 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 85 0x06 (0x26) pinc pinc7 pinc6 pinc5 pi nc4 pinc3 pinc2 pinc1 pinc0 page 86 0x05 (0x25) portb portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 page 85 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 85 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 85 0x02 (0x22) porta porta7 porta6 porta5 porta4 port a3 porta2 porta1 porta0 page 85 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 85 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 85 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 398 at90can128 4250e?can?12/04 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call k direct subroutine call pc k none 4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? cz, n,v,c,h1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 399 at90can128 4250e?can?12/04 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 none 2 cbi p,b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post-inc rd (rampz:z), rampz:z rampz:z+1 none 3 spm store program memory (z) r1:r0 none - mnemonics operands description operation flags #clocks 400 at90can128 4250e?can?12/04 in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 401 at90can128 4250e?can?12/04 ordering information note: this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa tion and minimum quantities. packaging information ordering code speed (mhz) power supply (v) package operation range product marking at90can128-16ai 16 2.7 - 5.5 64a industrial (-40 to +85c) at90can128-il at90can128-16mi 16 2.7 - 5.5 64m1 industrial (-40 to +85c) at90can128-il at90can128-16au 16 2.7 - 5.5 64a industrial (-40 to +85c) green at90can128-ul AT90CAN128-16MU 16 2.7 - 5.5 64m1 industrial (-40 to +85c) green at90can128-ul package type 64a 64-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 64m1 64-lead, quad flat no lead (qfn) 402 at90can128 4250e?can?12/04 tqfp64 index corner 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b 11?~13? pin 64 64 leads thin quad flat package notes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. symbol min nom mm max (2) (2) a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ min nom inch max ? ? . 047 . 002 ? . 006 . 037 . 039 . 041 . 620 . 630 . 640 . 547 . 551 . 555 . 620 . 630 . 640 . 547 . 551 . 555 . 012 ? . 018 . 004 ? . 008 . 018 ? . 030 . 0315 typ 403 at90can128 4250e?can?12/04 qfn64 1 index corner 2 3 64 63 62 64x b j k 64x l e exposed die at tac h pa d bottom view top view d e index corner a2 a1 0.08 a c seating plane side view b l e a2 n a1 d / e j / k a 6.47 0.80 min 6.57 nom mm 9.00 bsc 6.67 1.00 0.00 0.05 max . 255 . 031 min . 259 nom inch . 354 bsc 0.50 bsc . 020 bsc 64 . 263 0.40 0.45 0.50 . 016 . 018 . 020 0.17 0.25 0.27 . 007 . 010 . 011 . 039 . 000 . 002 0.75 1.00 . 029 . 039 max 64 leads quad flat no lead note: compliant jedec mo-220 404 at90can128 4250e?can?12/04 errata the revision letter in this section refers to the revision of the at90can128 device. rev c rev c (part marked: m90can128 - i ) asynchronous timer-2 wakes up without interrupt spi programming timing 1. asynchronous timer-2 wakes up without interrupt the asynchronous timer can wake from sleep without giving interrupt. the error only occurs if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this clear is done exactly when it is supposed to be set (compare match or overflow). only the interrupts flags are affected by the clear, not the signal witch is used to wake up the part. problem fix/workaround no known workaround, try to lock the code to avoid such a timing. 2. spi programming timing when the fuse high byte or the extended fuse byte has been written, it is necessary to wait the end of the programming using ?poll rdy/bsy ? instruction. if this instruc- tion is entered too speedily after the ?write fuse? instruction, the fuse low byte is written instead of high fuse /extended fuse byte. problem fix/workaround wait sometime before applying the ?poll rdy/bsy ? instruction. for 8mhz system clock, waiting 1 s is sufficient. rev a & b - rev a (part marked: m128can11 - el) - rev b (part marked: 90can128 - el) sporadic can error frames spike on twi pins when twi is enabled adc differential gain error with x1 & x10 amplification asynchronous timer-2 wakes up without interrupt spi programming timing idcode masks data from tdi input 6. sporadic can error frames when brp = 0 the can controller may desynchronize and send one error frame to ask for the retransmission of the incoming frame, even though it had no error. this is likely to occur with brp = 0 after long inter frame periods without synchroni- zation (low bus load). the can macro can still properly synchronize on frames following the error. problem fix/workaround set brp greater than 0 in canbt1. 5. spike on twi pins when twi is enabled 100 ns negative spike occurs on sda and scl pins when twi is enabled. 405 at90can128 4250e?can?12/04 problem fix/workaround no known workaround, enable at90can128 twi first versus the others nodes of the twi network. 4. adc differential gain error with x1 & x10 amplification gain error of - 4 lsb has been characterized on the part. problem fix/workaround software adjustment. 3. asynchronous timer-2 wakes up without interrupt the asynchronous timer can wake from sleep without giving interrupt. the error only occurs if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this clear is done exactly when it is supposed to be set (compare match or overflow). only the interrupts flags are affected by the clear, not the signal witch is used to wake up the part. problem fix/workaround no known workaround, try to lock the code to avoid such a timing. 2. spi programming timing when the fuse high byte or the extended fuse byte has been written, it is necessary to wait the end of the programming using ?poll rdy/bsy ? instruction. if this instruc- tion is entered too speedily after the ?write fuse? instruction, the fuse low byte is written instead of high fuse /extended fuse byte. problem fix/workaround wait sometime before applying the ?poll rdy/bsy ? instruction. for 8mhz system clock, waiting 1 s is sufficient. 1. idcode masks data from tdi input the jtag instruction idcode is not working correctly. data to succeeding devices are replaced by all-ones during update-dr. problem fix / workaround ? if at90can128 is the only device in the scan chain, the problem is not visible. ? select the device id register of the at90can128 by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. issue the bypass instruction to the at90can128 while reading the device id registers of preceding devices of the boundary scan chain. ? if the device ids of all devices in the boundary scan chain must be captured simultaneously, the at90can128 must be the first device in the chain. 406 at90can128 4250e?can?12/04 datasheet change log for at90can128 please note that the referring page numbers in this section are referring to this document. the referring revision in this section are referring to the document revision. changes from 4250d-07/04 to 4250e-12/04 1. information on phs2 segment of can bit timing (see ?bit timing? on page 235 , see ?baud rate? on page 236 and see ?can bit timing register 3 - canbt3? on page 252). 2. information on capacitors when using 32.768 khz crystal on xtal1 & 2 and tosc1 & 2 pins. 3. correction table 135. "serial programming instruction set" on page 340. 4. updated reset, bod & bandgap characteristics in section ?system control and reset? on page 47. 5. added curves in section ?at90can128 typical characteristics? on page 374. 6. updated characteristics in section ?electrical characteristics (1) ? on page 355. 7. updated errata device rev c. 8. changed ordering information. changes from 4250c-03/04 to 4250d-07/04 1. updated errata device rev a & b. changes from 4250b-02/04 to 4250c-03/04 1. changed part number to at90can128. 2. changed ordering information. changes from 4250a-10/03 to 4250b-02/04 1. modified product ordering information. 2. added errata section. 3. updated boundary-scan ieee 1149.1 (jtag) chapter. 4. updated assembler examples. i at90can128 4250e?can?12/04 table of contents features................................................................................................. 1 description ............................................................................................ 2 disclaimer .............................................................................................. 2 block diagram ...................................................................................................... 3 pin configurations ................................................................................ 4 pin descriptions.....................................................................................................6 about code examples .......................................................................................... 7 avr cpu core ...................................................................................... 8 introduction ........................................................................................................... 8 architectural overview.......................................................................................... 8 alu ? arithmetic logic unit.................................................................................. 9 status register ....................................................................................................10 general purpose register file ........................................................................... 11 stack pointer ...................................................................................................... 12 instruction execution timing............................................................................... 13 reset and interrupt handling.............................................................................. 13 memories ............................................................................................. 16 in-system reprogrammable flash program memory ........................................ 16 sram data memory............................................................................................17 eeprom data memory.......................................................................................19 i/o memory ..........................................................................................................24 external memory interface.................................................................................. 24 general purpose i/o registers............................................................................33 system clock ...................................................................................... 34 clock systems and their distribution .................................................................. 34 clock sources..................................................................................................... 35 default clock source .......................................................................................... 35 crystal oscillator..................................................................................................36 low-frequency crystal oscillator ........................................................................ 37 calibrated internal rc oscillator ........................................................................ 38 external clock..................................................................................................... 39 clock output buffer ............................................................................................ 40 timer/counter2 oscillator................................................................................... 40 system clock prescaler...................................................................................... 41 power management and sleep modes.............................................. 43 idle mode .............................................................................................................44 adc noise reduction mode............................................................................... 44 ii at90can128 4250e?can?12/04 power-down mode.............................................................................................. 44 power-save mode............................................................................................... 44 standby mode..................................................................................................... 45 minimizing power consumption ......................................................................... 45 system control and reset ................................................................. 47 internal voltage reference ................................................................................. 52 watchdog timer ..................................................................................................53 timed sequences for changing the configuration of the watchdog timer ....... 55 interrupts ............................................................................................. 56 interrupt vectors in at90can128 ...................................................................... 56 moving interrupts between application and boot space.................................... 59 i/o-ports............................................................................................... 61 introduction ......................................................................................................... 61 ports as general digital i/o ................................................................................ 62 alternate port functions ..................................................................................... 67 register description for i/o-ports........................................................................85 external interrupts.............................................................................. 88 timer/counter3/1/0 prescalers .......................................................... 91 overview............................................................................................................. 91 timer/counter0/1/3 prescalers register description ......................................... 92 8-bit timer/counter0 with pwm......................................................... 94 features.............................................................................................................. 94 overview............................................................................................................. 94 timer/counter clock sources............................................................................. 95 counter unit........................................................................................................ 95 output compare unit.......................................................................................... 96 compare match output unit ................................................................................98 modes of operation .............................................................................................99 timer/counter timing diagrams....................................................................... 102 8-bit timer/counter register description ......................................................... 104 16-bit timer/counter (timer/counter1 and timer/counter3)........ 108 features............................................................................................................ 108 overview........................................................................................................... 108 accessing 16-bit registers ................................................................................111 timer/counter clock sources............................................................................115 counter unit...................................................................................................... 115 input capture unit............................................................................................. 116 output compare units ...................................................................................... 118 compare match output unit ..............................................................................120 iii at90can128 4250e?can?12/04 modes of operation .......................................................................................... 121 timer/counter timing diagrams....................................................................... 128 16-bit timer/counter register description ........................................................131 8-bit timer/counter2 with pwm and asynchronous operation ... 140 features............................................................................................................ 140 overview........................................................................................................... 140 timer/counter clock sources........................................................................... 142 counter unit...................................................................................................... 142 output compare unit........................................................................................ 143 compare match output unit ..............................................................................145 modes of operation .......................................................................................... 145 timer/counter timing diagrams........................................................................150 8-bit timer/counter register description ..........................................................151 asynchronous operation of the timer/counter2 ............................................... 154 timer/counter2 prescaler..................................................................................158 output compare modulator - oc m ................................................. 160 overview........................................................................................................... 160 description........................................................................................................ 160 serial peripheral interface ? spi...................................................... 162 features............................................................................................................ 162 ss pin functionality...........................................................................................167 data modes .......................................................................................................170 usart (usart0 and usart1)....................................................... 171 features............................................................................................................ 171 dual usart ..................................................................................................... 171 overview........................................................................................................... 172 clock generation .............................................................................................. 173 serial frame ..................................................................................................... 175 usart initialization.......................................................................................... 176 data transmission ? usart transmitter .........................................................178 data reception ? usart receiver...................................................................180 asynchronous data reception ......................................................................... 184 multi-processor communication mode ..............................................................187 usart register description .............................................................................189 examples of baud rate setting........................................................................ 195 two-wire serial interface ................................................................. 199 features............................................................................................................ 199 two-wire serial interface bus definition........................................................... 199 data transfer and frame format ..................................................................... 200 multi-master bus systems, arbitration and synchronization ............................ 202 overview of the twi module .............................................................................205 iv at90can128 4250e?can?12/04 twi register description...................................................................................207 using the twi ................................................................................................... 211 transmission modes..........................................................................................214 multi-master systems and arbitration............................................................... 227 controller area network - can ....................................................... 229 features............................................................................................................ 229 can protocol .................................................................................................... 229 can controller...................................................................................................234 can channel.....................................................................................................235 message objects ...............................................................................................237 can timer .........................................................................................................240 error management.............................................................................................241 interrupts............................................................................................................243 can register description..................................................................................245 general can registers .................................................................................... 246 mob registers.................................................................................................. 254 examples of can baud rate setting ............................................................... 260 analog comparator .......................................................................... 262 overview........................................................................................................... 262 analog comparator register description ......................................................... 262 analog comparator multiplexed input .............................................................. 264 analog to digital converter - adc .................................................. 265 features............................................................................................................ 265 operation .......................................................................................................... 267 starting a conversion ....................................................................................... 267 prescaling and conversion timing ................................................................... 268 changing channel or reference selection ...................................................... 271 adc noise canceler......................................................................................... 272 adc conversion result.................................................................................... 277 adc register description................................................................................. 279 jtag interface and on-chip debug system .................................. 284 features............................................................................................................ 284 overview........................................................................................................... 284 test access port ? tap.................................................................................... 284 tap controller .................................................................................................. 286 using the boundary-scan chain ....................................................................... 287 using the on-chip debug system .................................................................... 287 on-chip debug specific jtag instructions ...................................................... 288 on-chip debug related register in i/o memory .............................................. 288 using the jtag programming capabilities ...................................................... 289 bibliography ...................................................................................................... 289 v at90can128 4250e?can?12/04 boundary-scan ieee 1149.1 (jtag) ............................................... 290 features............................................................................................................ 290 system overview.............................................................................................. 290 data registers .................................................................................................. 290 boundary-scan specific jtag instructions ...................................................... 292 boundary-scan related register in i/o memory .............................................. 293 boundary-scan chain ....................................................................................... 294 at90can128 boundary-scan order .................................................................305 boundary-scan description language files ..................................................... 310 boot loader support ? read-while-w rite self-programming ...... 311 features............................................................................................................ 311 application and boot loader flash sections .................................................... 311 read-while-write and no read-while-write flash sections........................... 311 boot loader lock bits....................................................................................... 314 entering the boot loader program ................................................................... 315 addressing the flash during self-programming .............................................. 317 self-programming the flash ............................................................................. 318 memory programming ...................................................................... 325 program and data memory lock bits............................................................... 325 fuse bits........................................................................................................... 326 signature bytes ................................................................................................ 328 calibration byte ................................................................................................ 328 parallel programming overview ........................................................................329 parallel programming ....................................................................................... 331 spi serial programming overview ....................................................................337 spi serial programming ................................................................................... 338 jtag programming overview ...........................................................................342 electrical characteristics (1) .............................................................. 355 absolute maximum ratings*............................................................................. 355 dc characteristics............................................................................................ 356 external clock drive characteristics .................................................................358 two-wire serial interface characteristics ..........................................................359 spi timing characteristics ................................................................................361 can physical layer characteristics ................................................................. 362 adc characteristics ......................................................................................... 363 external data memory characteristics ..............................................................365 parallel programming characteristics ...............................................................371 at90can128 typical characteristics............................................. 374 active supply current ....................................................................................... 374 idle supply current ........................................................................................... 377 power-down supply current............................................................................. 379 power-save supply current.............................................................................. 380 vi at90can128 4250e?can?12/04 standby supply current.................................................................................... 381 pin pull-up ........................................................................................................ 381 pin driver strength ........................................................................................... 383 bod thresholds and analog comparator offset ............................................. 385 internal oscillator speed .................................................................................. 387 current consumption of peripheral units ......................................................... 389 current consumption in reset and reset pulse width.................................... 392 register summary ............................................................................ 394 instruction set summary ................................................................. 398 ordering information........................................................................ 401 packaging information ..................................................................... 401 tqfp64 ............................................................................................................ 402 qfn64 .............................................................................................................. 403 errata ................................................................................................. 404 rev c................................................................................................................ 404 rev a & b ......................................................................................................... 404 datasheet change log for at90can128 ....................................... 406 changes from 4250d-07/04 to 4250e-12/04.................................................... 406 changes from 4250c-03/04 to 4250d-07/04.................................................... 406 changes from 4250b-02/04 to 4250c-03/04.................................................... 406 changes from 4250a-10/03 to 4250b-02/04 .................................................... 406 table of contents ................................................................................. 1 printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions locate d on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implicati on. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4250e?can?12/04 /xm ? atmel corporation 2004. all rights reserved. atmel?, logo and combinations thereof are registered trademarks, and everywhere you are(sm) are the trademarks of atmel corporatio n or its subsidiaries. other terms and product names may be trademarks of others. |
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